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81. 发明授权

US08450155B2 Method for introducing channel stress and field effect transistor fabricated by the same 有权
标题翻译：引入沟道应力的方法和由其制造的场效应晶体管
公开(公告)号：US08450155B2
公开(公告)日：2013-05-28
申请号：US13131602
申请日：2011-04-01
申请人： Ru Huang , Quanxin Yun , Xia An , Xing Zhang
发明人： Ru Huang , Quanxin Yun , Xia An , Xing Zhang
IPC分类号： H01L21/332 , H01L21/335 , H01L21/8232 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/7848 , H01L29/6653 , H01L29/66636 , H01L29/7833 , H01L29/7843
摘要： The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased.
摘要翻译：本发明涉及CMOS超大规模集成电路，并且提供了一种引入沟道应力的方法和由其制造的场效应晶体管。根据本发明，应变电介质层介于源极/漏极区域和场效应晶体管的衬底之间，并且通过直接接触衬底的应变介电层在沟道中诱发应变，从而改善信道的载波移动性和设备的性能。本发明的具体效果包括：通过使用具有拉伸应变的应变电介质层，可以在沟道中诱发拉伸应变，以增加通道的电子迁移率; 可以通过使用具有压缩应变的应变电介质层在沟道中诱发压缩应变，以增加通道的空穴迁移率。根据本发明，不仅引入通道应力的有效性，而且基本上也提高了场效应晶体管的器件结构，从而增加了抑制器件的短沟道效应的能力。

82. 发明授权

US08372752B1 Method for fabricating ultra-fine nanowire 有权
标题翻译：超细纳米线的制造方法
公开(公告)号：US08372752B1
公开(公告)日：2013-02-12
申请号：US13543704
申请日：2012-07-06
申请人： Ru Huang , Shuai Sun , Yujie Al , Jiewen Fan , Runsheng Wang , Xiaoyan Xu
发明人： Ru Huang , Shuai Sun , Yujie Al , Jiewen Fan , Runsheng Wang , Xiaoyan Xu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： B82Y40/00 , H01L29/0676
摘要： Disclosed herein is a method for fabricating an ultra fine nanowire, which relates to a manufacturing technology of a microelectronic semiconductor transistor. This method obtains a suspended ultra fine nanowire base on a combination of a mask blocking oxidation process and a stepwise oxidation process. A diameter of the suspended ultra fine nanowire fabricated by this method is precisely controlled to 20 nm by controlling a thickness of a deposited silicon nitride film and a time and temperature of the two oxidation process. Since a speed of a dry oxidation process is slower, the size of the final nanowire may be precisely controlled. This method can be used to fabricate an ultra fine nanowire with a lower cost and a higher applicability.
摘要翻译：本文公开了一种制造超细纳米线的方法，涉及微电子半导体晶体管的制造技术。该方法通过掩模阻挡氧化工艺和逐步氧化工艺的组合获得悬浮的超细纳米线基底。通过控制沉积的氮化硅膜的厚度和两个氧化过程的时间和温度，将通过该方法制造的悬浮超细纳米线的直径精确控制为20nm。由于干燥氧化工艺的速度较慢，可以精确地控制最终纳米线的尺寸。该方法可用于制造具有较低成本和较高适用性的超细纳米线。

83. 发明申请

US20120267700A1 TUNNELING CURRENT AMPLIFICATION TRANSISTOR 有权
标题翻译：隧道电流放大晶体管
公开(公告)号：US20120267700A1
公开(公告)日：2012-10-25
申请号：US13255087
申请日：2011-05-26
申请人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
发明人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
IPC分类号： H01L29/788
CPC分类号： H01L29/7391
摘要： The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base. As compared with the conventional TFET, the tunneling current amplification transistor of the present invention can increase the on-current of the device effectively and increase the driving capability of the device.
摘要翻译：本发明公开了一种隧道电流放大晶体管，其涉及CMOS超大规模半导体集成电路（ULSI）中的场效应晶体管逻辑器件的面积。隧道电流放大晶体管包括半导体衬底，栅极电介质层，发射极，漏极，浮动隧道基极和控制栅极，其中漏极，浮动隧道基极和控制栅极形成传统的TFET结构，发射极的掺杂类型与浮动隧道基体的掺杂类型相反。发射极的位置相对于漏极在浮动基底的另一侧。发射极和浮动隧道基底之间的半导体类型与浮动隧道基底的相同。与常规TFET相比，本发明的隧道电流放大晶体管可以有效地增加器件的导通电流，并提高器件的驱动能力。

84. 发明申请

US20120243313A1 SEMICONDUCTOR MEMORY ARRAY AND METHOD FOR PROGRAMMING THE SAME 有权
标题翻译：半导体存储器阵列及其编程方法
公开(公告)号：US20120243313A1
公开(公告)日：2012-09-27
申请号：US13146005
申请日：2011-04-21
申请人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
发明人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.
摘要翻译：本发明提供一种闪存阵列结构及其编程方法，涉及超大规模集成电路制造技术中非易失性存储器的技术领域。本发明的闪速存储器阵列包括连接到存储单元的存储单元，字线和位线，其中连接到存储单元的控制栅极的字线和连接到存储单元的漏极端子的位线不垂直相互交叉但彼此成角度; 沿两个位线之间的通道方向彼此相邻的两个存储单元的控制栅极分别由两个字线控制，其漏极端分别由两个位线控制，并且其源极端子被共享。本发明还提供了一种用于编程闪存阵列结构的方法，其可以实现具有低功耗的编程。

85. 发明申请

US20120187976A1 METHOD FOR TESTING TRAP DENSITY OF GATE DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE HAVING NO SUBSTRATE CONTACT 有权
标题翻译：用于测试无基板接触的半导体器件中栅极介电层的阱密度的方法
公开(公告)号：US20120187976A1
公开(公告)日：2012-07-26
申请号：US13382415
申请日：2011-09-29
申请人： Ru Huang , Jibin Zou , Runsheng Wang , Jiewen Fan , Changze Liu , Yangyuan Wang
发明人： Ru Huang , Jibin Zou , Runsheng Wang , Jiewen Fan , Changze Liu , Yangyuan Wang
IPC分类号： G01R31/26
CPC分类号： H01L22/14 , G01R31/2621 , G01R31/2642 , H01L2924/0002 , H01L2924/00
摘要： A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges. After that, the following steps are repeated sequentially to form a loop by changing the bias settings: 1) carriers flow into the channel through the source and the drain to form an inversion layer, and a portion of carriers are confined by the traps in the gate dielectric layer; 2) carriers of the inversion layer flow back to the source and the drain respectively, whereas the carriers confined by the traps in the gate dielectric layer do not flow back to the channel; 3) carriers confined by the traps in the gate dielectric layer flow out through the drain terminal only; and the trap density of the gate dielectric layer are calculated according to the period of the loop, the size of the channel of the device, and DC currents at the source and the drain. The method is simple and effective and is easy to setup the instruments with a low cost. The method is applicable to be used in testing traps in the gate dielectric layer of the devices that have no substrate contact, especially the surrounding-gate device.
摘要翻译：本发明提供了一种在没有衬底接触的半导体器件的栅介质层中测试阱密度的方法。器件的源极和漏极是双向对称的，连接到源极和漏极的测试仪器的探头和电缆是双边对称的。首先，控制栅极，源极和漏极处的偏置设置，使得器件处于不形成反型层的初始状态，并且栅极电介质层中的陷阱对电荷没有施加约束效应。之后，顺序重复以下步骤，通过改变偏置设置来形成一个环路：1）载流子通过源极和漏极流入沟道，形成一个反型层，一部分载流子被陷阱限制在栅介质层; 2）反转层的载流子分别流回到源极和漏极，而由栅极电介质层中的陷阱限制的载流子不流回到沟道; 3）由栅极电介质层中的陷阱限制的载流子仅通过漏极端子流出; 并且根据环路的周期，器件的通道的尺寸以及源极和漏极处的直流电流来计算栅极介电层的陷阱密度。该方法简单有效，易于以低成本设置仪器。该方法适用于在不与衬底接触的器件的栅极电介质层中测试陷阱，特别是周围栅极器件。

86. 发明申请

US20120187495A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120187495A1
公开(公告)日：2012-07-26
申请号：US13201618
申请日：2010-09-25
申请人： Xia An , Yue Guo , Quanxin Yun , Ru Huang , Xing Zhang
发明人： Xia An , Yue Guo , Quanxin Yun , Ru Huang , Xing Zhang
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L29/16 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. According to the method for fabricating a semiconductor device, through the implantation of silicon impurities, appropriate stress may be introduced into the germanium channel effectively by the mismatch of lattices in the source and drain regions, so that the mobility of electrons in the channel is enhanced and the performance of the device is improved.
摘要翻译：本发明提供了一种半导体器件及其制造方法，其中该方法包括：在多个有源区之间提供具有多个有源区和器件隔离区的锗基半导体衬底，其中栅介电层并且栅极电介质层上的栅极设置在有源区上，有源区包括源极和漏极延伸区以及深的源极和漏极区; 对源极和漏极延伸区域执行第一离子注入工艺，其中在第一离子注入工艺中注入的离子包括硅或碳; 对源极和漏极延伸区域执行第二离子注入工艺; 相对于深源极和漏极区域执行第三离子注入工艺; 对已进行第三离子注入工艺的锗基半导体衬底进行退火处理。根据制造半导体器件的方法，通过硅杂质的注入，可以通过栅极和漏极区域中的晶格失配有效地将适当的应力引入锗通道中，使得沟道中电子的迁移率增强并提高了设备的性能。

87. 发明申请

US20120113726A1 FLASH MEMORY AND FABRICATION METHOD AND OPERATION METHOD FOR THE SAME 有权
标题翻译：闪存及其制造方法和操作方法
公开(公告)号：US20120113726A1
公开(公告)日：2012-05-10
申请号：US13321120
申请日：2011-03-07
申请人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
发明人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
IPC分类号： G11C16/26 , H01L21/336 , H01L27/115
CPC分类号： H01L27/11556 , H01L29/7391 , H01L29/7889 , H01L29/8616
摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.
摘要翻译：本发明公开了一种闪存及其制作方法及其操作方法。闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

88. 发明申请

US20060141025A1 Methods and compositions for delivery of catecholic butanes for treatment of tumors 失效
标题翻译：用于递送儿茶酚丁烷用于治疗肿瘤的方法和组合物
公开(公告)号：US20060141025A1
公开(公告)日：2006-06-29
申请号：US11284111
申请日：2005-11-21
申请人： Ru Huang , Richard Park , Chih-Chuan Chang , Yu-Chuan Liang , David Mold , Elaine Lin , Jonathan Heller , Neil Frazer
发明人： Ru Huang , Richard Park , Chih-Chuan Chang , Yu-Chuan Liang , David Mold , Elaine Lin , Jonathan Heller , Neil Frazer
IPC分类号： A61K9/48 , A61K31/24 , A61K31/205
CPC分类号： A61K9/5153 , A61K9/0019 , A61K9/0024 , A61K9/0043 , A61K9/0078 , A61K9/1075 , A61K9/1271 , A61K31/205 , A61K31/24
摘要： The present invention provides kits, methods and compositions for the treatment of tumor and other proliferative diseases such as tumors. The compositions herein contain a substantially pure preparation of at least one catecholic butane, including, for example, NDGA compounds in a pharmaceutically acceptable carrier or excipient. The catecholic butane such as NDGA or its derivatives are administered to one or more subjects in need of treatment by a route other than direct injection into the affected tissues or topical application on affected tissues.
摘要翻译：本发明提供用于治疗肿瘤和其它增殖性疾病如肿瘤的试剂盒，方法和组合物。本文的组合物含有至少一种儿茶酚丁烷的基本上纯的制剂，包括例如药学上可接受的载体或赋形剂中的NDGA化合物。将诸如NDGA或其衍生物的儿茶酚丁烷通过除了直接注射到受影响组织内的途径或受影响组织上的局部施用而施用于需要治疗的一个或多个受试者。

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