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81. 发明申请

US20060145193A1 Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation 有权
标题翻译：双模解码器电路，集成电路存储器阵列及其相关操作方法
公开(公告)号：US20060145193A1
公开(公告)日：2006-07-06
申请号：US11026493
申请日：2004-12-30
申请人： Kenneth So , Luca Fasoli , Roy Scheuerlein
发明人： Kenneth So , Luca Fasoli , Roy Scheuerlein
IPC分类号： H01L27/10 , G11C5/06
CPC分类号： G11C8/10
摘要： In an embodiment of the invention an integrated circuit includes a memory array having a first plurality of decoded lines traversing across the memory array and a pair of dual-mode decoders, each decoder coupled to each of the plurality of decoded lines a respective location along said decoded lines, such as at opposite ends thereof. Both decoder circuits receive like address information. Normally both decoder circuits operate in a forward decode mode to decode the address information and drive a selected one of the decoded lines. During a test mode, one decoder is enabled in a reverse decode mode while the other decoder remains in a forward decode mode to verify proper decode operation and integrity of the decoded lines between the decoders.
摘要翻译：在本发明的一个实施例中，集成电路包括存储器阵列，该存储器阵列具有遍及存储器阵列的第一多条解码线和一对双模式解码器，每个解码器耦合到多条解码线中的每条解码线，解码线，例如在其相对端。两个解码器电路都接收类似的地址信息。通常两个解码器电路都以正向解码模式工作，以对地址信息进行解码并驱动所选择的解码行之一。在测试模式期间，一个解码器以反向解码模式使能，而另一个解码器保持在正向解码模式，以验证解码器之间解码线路的正确解码操作和完整性。

82. 发明申请

US20060133125A1 Apparatus and method for memory operations using address-dependent conditions 有权
标题翻译：用于使用地址相关条件的存储器操作的装置和方法
公开(公告)号：US20060133125A1
公开(公告)日：2006-06-22
申请号：US11015440
申请日：2004-12-17
申请人： Kenneth So , Luca Fasoli , Roy Scheuerlein
发明人： Kenneth So , Luca Fasoli , Roy Scheuerlein
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1677
摘要： An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.
摘要翻译：公开了一种包括多个字线和字线驱动器，多个位线和位线驱动器以及耦合在各个字线和位线之间的多个存储器单元的装置。该装置还包括电路，用于基于相对于字线驱动器和位线驱动器中的一个或两者的存储单元的位置来选择写入和/或读取条件以应用于存储器单元。该装置还可以包括电路，其可操作以基于相对于字线和/或位线驱动器的存储器单元位置来并行地选择要编程的多个存储器单元。

83. 发明申请

US20050078514A1 Multiple twin cell non-volatile memory array and logic block structure and method therefor 有权
标题翻译：多个单元非易失性存储器阵列及其逻辑块结构及其方法
公开(公告)号：US20050078514A1
公开(公告)日：2005-04-14
申请号：US10675212
申请日：2003-09-30
申请人： Roy Scheuerlein , Luca Fasoli , Mark Johnson
发明人： Roy Scheuerlein , Luca Fasoli , Mark Johnson
IPC分类号： G11C8/10 , G11C8/14 , G11C11/34 , G11C16/10 , G11C16/16
CPC分类号： G11C15/046 , G11C8/10 , G11C8/14 , G11C16/10 , G11C16/16
摘要： Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays. Such arrays may be configured as a memory to store data, or configured to perform threshold logic, or configured as a content addressable memory array.
摘要翻译：非常密集的存储单元结构提供了用于实现内存和逻辑功能的新数组结构。示例性非易失性存储器阵列包括被配置为在读取操作模式下在逻辑上相同的第一多个X线，并且每个X线与与至少一个Y线编号的第一Y线组相关联。第一多个X线中的每一个也可以与编号至少一个Y线的第二Y线组相关联。在一些实施例中，第一和第二Y线组可以以读取模式同时选择，并且当这样选择时，它们分别耦合到读出放大器电路的真实和补码输入。这样的Y线组可以仅编号一条Y线，或者可以编号多于一条Y线。可以在2D或3D存储器阵列中使用许多类型的存储单元，例如各种无源元件单元和EEPROM单元。这样的阵列可以被配置为存储数据，或被配置为执行阈值逻辑或被配置为内容可寻址存储器阵列的存储器。

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