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81. 发明授权

US07310788B2 Sample probability of fault function determination using critical defect size map 失效
标题翻译：使用关键缺陷尺寸图的故障函数确定的样本概率
公开(公告)号：US07310788B2
公开(公告)日：2007-12-18
申请号：US10906549
申请日：2005-02-24
申请人： Robert J. Allen , Mervyn Y. Tan
发明人： Robert J. Allen , Mervyn Y. Tan
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/504
摘要： Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical area determinations can also be supplied based on the exact or sample POF functions. The invention provides a less computationally complex and storage-intensive methodology.
摘要翻译：使用关键缺陷尺寸图确定故障概率（POF）功能的方法，系统和程序产品。提供精确或样本POF功能的方法。也可以根据POF功能的准确或取样来提供关键区域测定。本发明提供了较少的计算复杂性和存储密集型方法。

82. 发明授权

US07240306B2 Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing 有权
标题翻译：使用Voronoi图和形状偏置的集成电路布局临界区域确定
公开(公告)号：US07240306B2
公开(公告)日：2007-07-03
申请号：US10906553
申请日：2005-02-24
申请人： Robert J. Allen , Peter K. Chan , Evanthia Papadopoulou , Sarah C. Prue , Mervyn Y. Tan
发明人： Robert J. Allen , Peter K. Chan , Evanthia Papadopoulou , Sarah C. Prue , Mervyn Y. Tan
IPC分类号： G06F17/50 , G06F19/00 , G06F17/10 , G06F11/00 , G06K9/03 , G06K9/52
CPC分类号： G06F17/5081
摘要： Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.
摘要翻译：用于使用Voronoi图和形状偏置来确定集成电路布局的区域中的临界区域的方法，系统和程序产品。该方法包括以下步骤：基于该区域的布局几何形状并结合形状偏差产生偏置Voronoi图; 并使用偏倚的Voronoi图确定该地区的关键区域。

83. 发明授权

US07143371B2 Critical area computation of composite fault mechanisms using voronoi diagrams 有权
标题翻译：使用voronoi图的复合故障机制的关键区域计算
公开(公告)号：US07143371B2
公开(公告)日：2006-11-28
申请号：US10709293
申请日：2004-04-27
申请人： Robert J. Allen , Evanthia Papadopoulou , Mervyn Yee-Min Tan
发明人： Robert J. Allen , Evanthia Papadopoulou , Mervyn Yee-Min Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.
摘要翻译：公开了一种在集成电路设计中确定与不同类型的故障机制相关联的关键区域的方法。本发明通过为单个故障机制的关键区域构建单独的Voronoi图和基于各个Voronoi图的复合Voronoi图来实现。本发明基于复合Voronoi图计算了集成电路设计复合故障机理的关键区域。

84. 发明授权

US06967185B2 Synthesis of noble metal, sulphide catalysts in a sulfide ion-free aqueous environment 有权
公开(公告)号：US06967185B2
公开(公告)日：2005-11-22
申请号：US10877005
申请日：2004-06-24
申请人： Robert J. Allen , Andrea F. Gulla
发明人： Robert J. Allen , Andrea F. Gulla
IPC分类号： B01J21/18 , B01J23/40 , B01J27/045 , B01J27/051 , B01J35/10 , B01J37/20 , C25B11/00 , C25B11/03 , C25B11/04 , H01M4/00 , H01M4/86 , H01M4/88 , H01M4/90 , B01J27/02 , B01J27/043
CPC分类号： B01J21/18 , B01J23/40 , B01J27/045 , B01J27/051 , B01J27/0515 , B01J35/1014 , B01J37/20 , C25B11/035 , C25B11/0447 , H01M4/8605 , H01M4/8807 , H01M4/90 , H01M4/9083
摘要： A noble metal sulfide catalyst obtained by reaction of a precursor of at least one noble metal with a thionic species in an aqueous environment essentially free of sulfide ions useful as an electrocatalyst in the depolarized electrolysis of hydrochloric acid.

85. 发明授权

US06790303B2 Apparatus and method for sealing an envelope 有权
标题翻译：用于密封信封的装置和方法
公开(公告)号：US06790303B2
公开(公告)日：2004-09-14
申请号：US10023151
申请日：2001-12-17
申请人： Robert J. Allen , Carl R Chapman , David K Halden , Thomas M Lyga , Michael Roche
发明人： Robert J. Allen , Carl R Chapman , David K Halden , Thomas M Lyga , Michael Roche
IPC分类号： B43M500
CPC分类号： B43M5/042 , Y10T156/1002 , Y10T156/1051
摘要： An envelope with its flap in an open position is driven along a transport path by first transport means (31a) at a first location. When the crease line between the flap and the body of the envelope reaches a predetermined location along the transport path, buckling means (31b, 53) engage the envelope from opposite sides at a second location, spaced apart from the first location, such as to cause the envelope to buckle laterally of the transport path and be partially closed. The buckling envelope with its crease line leading is then received by sealing means (31a, 31b), by means of which the envelope fully closed.
摘要翻译：具有其挡板处于打开位置的信封通过第一位置处的第一传送装置（31a）沿传送路径被驱动。当折翼与信封的主体之间的折痕线沿着传送路径到达预定位置时，弯曲装置（31b，53）在与第一位置间隔开的第二位置处的相对侧与外壳接合，例如导致信封在传送路径的侧面弯曲并部分关闭。然后用密封装置（31a，31b）接收其折痕线前导的弯曲包络，通过该装置将信封完全关闭。

86. 发明授权

US06751744B1 Method of integrated circuit design checking using progressive individual network analysis 有权
标题翻译：集成电路设计检查方法采用渐进式单独网络分析
公开(公告)号：US06751744B1
公开(公告)日：2004-06-15
申请号：US09475799
申请日：1999-12-30
申请人： Robert J. Allen , John M. Cohn , David J. Hathaway
发明人： Robert J. Allen , John M. Cohn , David J. Hathaway
IPC分类号： G06F112
CPC分类号： G06F17/504 , G06F2217/78
摘要： A method for checking integrated circuit designs comprising the steps of calculating a first performance parameter by analyzing the network's sensitivity to a signal applied to the network; comparing the first performance parameter to one or more rules to determine a first pass condition and writing the value of first performance parameter to a netlist file in response to a pass to the first pass condition; followed by calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing the second performance parameter to the netlist file in response to a pass to said second pass condition or writing an error flag to the netlist file in response to a fail to said second pass condition is disclosed. The method, at each step, decides if a quick to calculate parameter provides sufficient design margin or if a more accurate but longer to calculate parameter is required.
摘要翻译：一种用于检查集成电路设计的方法，包括以下步骤：通过分析网络对施加到网络的信号的灵敏度来计算第一性能参数; 将所述第一性能参数与一个或多个规则进行比较以确定第一通过条件，并响应于所述第一通过条件的传递将所述第一性能参数的值写入网表文件; 随后基于第一网络模型计算第二性能参数，以响应于所述第一通过条件的失败来确定第二通过条件，并响应于所述第二通过条件的通过将所述第二性能参数写入所述网表文件，或公开了响应于所述第二通过条件的失败向网表文件写入错误标志。该方法在每个步骤中决定快速计算参数是否提供足够的设计余量，或者是否需要更准确但更长的计算参数。

87. 发明授权

US06673127B1 Method of forming robust metal, metal oxide, and metal alloy layers on ion-conductive polymer membranes 有权
标题翻译：在离子导电聚合物膜上形成牢固的金属，金属氧化物和金属合金层的方法
公开(公告)号：US06673127B1
公开(公告)日：2004-01-06
申请号：US09710635
申请日：2000-11-09
申请人： Robert J. Allen , James R. Giallombardo , Emory S. DeCastro
发明人： Robert J. Allen , James R. Giallombardo , Emory S. DeCastro
IPC分类号： H01M488
CPC分类号： H01M4/8871 , C23C14/022 , C25B9/10 , G01N27/404 , H01M4/8817 , H01M4/9016 , H01M4/92 , H01M8/0245 , H01M8/1004 , H01M8/1009 , H01M8/1016 , H01M2300/0082 , Y10T29/49108 , Y10T29/49115
摘要： An ion beam-assisted deposition process for preparing a membrane-electrode structure is described wherein a layer of liquid ionomer is applied to the surface of a carbon cloth gas diffusion electrode structure. The coated structure is heated to form an ionomer film on the cloth electrode and the resulting structure is treated with a metal or metal oxide ion-beam having an energy between 500-2000 eV. The process forms a carbon cloth supported metal or a carbon metal oxide ionomer film membrane-electrode structure.
摘要翻译：描述了一种用于制备膜 - 电极结构的离子束辅助沉积方法，其中将一层液体离聚物施加到碳布气体扩散电极结构的表面。加热涂层结构以在布电极上形成离聚物膜，并且所得结构用能量在500-2000eV之间的金属或金属氧化物离子束进行处理。该方法形成碳布支撑金属或碳金属氧化物离聚物膜膜电极结构。

88. 发明授权

US06444602B1 Structures and methods of manufacture for gas diffusion electrodes and electrode components 有权
标题翻译：气体扩散电极和电极组件的制造结构和方法
公开(公告)号：US06444602B1
公开(公告)日：2002-09-03
申请号：US09715458
申请日：2000-11-14
申请人： Michael DeMarinis , Emory S. De Castro , Robert J. Allen , Khaleda Shaikh
发明人： Michael DeMarinis , Emory S. De Castro , Robert J. Allen , Khaleda Shaikh
IPC分类号： H01M488
CPC分类号： H01M8/1004 , C25B11/035 , H01M4/8807 , H01M4/8828 , H01M4/886 , H01M4/8882 , H01M4/8885 , H01M4/8896 , H01M4/926 , H01M4/96 , H01M8/0232 , H01M8/0234 , H01M8/0239 , H01M8/0243 , H01M8/0245 , H01M2300/0082 , Y02P70/56
摘要： Gas Diffusion Electrodes (GDEs) play a pivotal role in clean energy production as well as in electrochemical processes and sensors. These gas-consuming electrodes are typically designed for liquid electrolyte systems such as phosphoric acid and alkaline fuel cells, and are commercially manufactured by hand or in a batch process. However, GDEs using the new electrolytes such as conductive polymer membranes demand improved electrode structures. This invention pertains to GDEs and gas diffusion media with new structures for systems using membrane electrode assemblies (MEAs), and automated methods of manufacture that lend themselves to continuous mass production. Unexpected improvements in gas and vapor transport through the electrode are realized by incorporating a new dispersion process in the construction, reformulating the applied mix with solution additives, and creating a novel coating structure on a conductive web. Furthermore, combining these changes with a judicious choice in coating methodology allows one to produce these materials in a continuous automated fashion.
摘要翻译：气体扩散电极（GDEs）在清洁能源生产以及电化学过程和传感器方面发挥关键作用。这些耗气电极通常设计用于诸如磷酸和碱性燃料电池的液体电解质系统，并且可以手工或间歇工艺制造。然而，使用诸如导电聚合物膜的新电解质的GDE需要改进的电极结构。本发明涉及具有用于使用膜电极组件（MEA）的系统的新结构的GDE和气体扩散介质，以及适用于连续质量的自动化制造方法生产。通过在结构中引入新的分散方法，用溶液添加剂重新配制施用的混合物，并在导电网上形成新的涂层结构，可以实现通过电极的气体和蒸汽输送的意想不到的改进。此外，将这些变化与涂层方法的明智选择结合起来，可以以连续的自动化方式生产这些材料。

89. 发明授权

US5958197A Catalysts for gas diffusion electrodes 失效
标题翻译：用于气体扩散电极的催化剂
公开(公告)号：US5958197A
公开(公告)日：1999-09-28
申请号：US013080
申请日：1998-01-26
申请人： Robert J. Allen , Daniel Czerwiec , James R. Giallombardo , Khaleda Shaikh
发明人： Robert J. Allen , Daniel Czerwiec , James R. Giallombardo , Khaleda Shaikh
IPC分类号： B01J23/46 , C25B11/03 , C25B11/08 , H01M4/88 , H01M4/90 , H01M4/92 , C25B11/00
CPC分类号： H01M4/92 , C25B11/035
摘要： A gas diffusion electrode comprising an electrically conductive web provided on at least one side thereof with a coating containing a rhodium--rhodium oxide catalyst on a carbon black support and a method for the preparation of the rhodium--rhodium oxide catalyst.
摘要翻译：一种气体扩散电极，包括在其至少一侧上具有在炭黑载体上含有铑 - 铑氧化物催化剂的涂层的导电网和用于制备铑 - 铑氧化物催化剂的方法。

90. 发明授权

US5300206A Antipercolation gas-diffusion electrode and method of making same 失效
标题翻译：反相气扩散电极及其制造方法
公开(公告)号：US5300206A
公开(公告)日：1994-04-05
申请号：US924094
申请日：1992-08-03
申请人： Robert J. Allen , Ravindra J. Vora , Michael De Marinis
发明人： Robert J. Allen , Ravindra J. Vora , Michael De Marinis
IPC分类号： C25B11/03 , C25C7/02 , H01M4/86 , H01M4/88 , C25B11/04 , C09J5/10
CPC分类号： H01M4/86
摘要： A gas diffusion electrode is provided with antipercolation coating by bonding a free-standing film, e.g. of polysulfone or polypropylene, to a catalyzed carbon cloth utilizing a filled polysulfone/N-MP adhesive which is subjected to solvent exchange with water by either a thermal bonding as in the case of a free-standing microporous polysulfone film or mechanical bonding as in the case of a commercial microporous polypropylene film.
摘要翻译：气体扩散电极通过粘合独立的膜，例如，的聚砜或聚丙烯，使用填充聚砜/ N-MP粘合剂的催化碳布，其通过热粘合与水进行溶剂交换，如在独立的微孔聚砜膜或机械粘合的情况下，如商业微孔聚丙烯薄膜的情况。

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