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81. 发明申请

US20130341596A1 NANOWIRE FET AND FINFET 审中-公开
标题翻译： NANOWIRE FET和FINFET
公开(公告)号：US20130341596A1
公开(公告)日：2013-12-26
申请号：US13548554
申请日：2012-07-13
申请人： Josephine B. Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L21/845 , B82Y10/00 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A complimentary metal oxide semiconductor (CMOS) device includes a wafer having a buried oxide (BOX) layer having a first region with a first thickness and a second region with a second thickness, the first thickness is less than the second thickness, a nanowire field effect transistor (FET) arranged on the BOX layer in the first region, the nanowire FET, and a finFET arranged on the BOX layer in the second region.
摘要翻译：互补金属氧化物半导体（CMOS）器件包括具有掩埋氧化物（BOX）层的晶片，其具有第一厚度的第一区域和具有第二厚度的第二区域，第一厚度小于第二厚度，纳米线场布置在第一区域中的BOX层上的效应晶体管（FET），纳米线FET和布置在第二区域中的BOX层上的finFET。

82. 发明授权

US08580624B2 Nanowire FET and finFET hybrid technology 失效
标题翻译：纳米线FET和finFET混合技术
公开(公告)号：US08580624B2
公开(公告)日：2013-11-12
申请号：US13286311
申请日：2011-11-01
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Leland Chang , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L27/1211 , B82Y10/00 , B82Y40/00 , H01L21/3247 , H01L21/845 , H01L29/0673 , H01L29/42392 , H01L29/66469 , H01L29/78696
摘要： Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.
摘要翻译：提供了混合纳米线FET和FinFET器件及其制造方法。一方面，制造具有纳米线FET和finFET的CMOS电路的方法包括以下步骤。提供了在BOX上具有活性层的晶片。有源层的第一区域变薄。有机平面化层沉积在有源层上。使用第一硬掩模在有源层的第一区域中蚀刻纳米线和焊盘。纳米线悬挂在BOX上。使用第二硬掩模在活性层的第二区域中蚀刻金箔。形成围绕每个纳米线的至少一部分的第一栅极堆叠。形成第二栅极堆叠，覆盖每个散热片的至少一部分。在纳米线，焊盘和鳍片的暴露部分上生长外延材料。

83. 发明申请

US20130292701A1 Doped Core Trigate FET Structure and Method 有权
标题翻译：掺杂核心追踪FET结构和方法
公开(公告)号：US20130292701A1
公开(公告)日：2013-11-07
申请号：US13461935
申请日：2012-05-02
申请人： Sarunya Bangsaruntip , Siyuranga O. Koswatta , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Siyuranga O. Koswatta , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/772 , H01L21/02 , H01L21/20
CPC分类号： H01L29/772 , H01L29/66795 , H01L29/7854
摘要： Techniques for fabricating a field effect transistor (FET) device having a doped core and an undoped or counter-doped epitaxial shell are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A wafer is provided having a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon. At least one fin core is formed in the wafer. Ion implantation is used to dope the fin core. Corners of the fin core are reshaped to make the corners rounded or faceted. An epitaxial shell is grown surrounding the fin core, wherein the epitaxial shell includes a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon.
摘要翻译：提供了用于制造具有掺杂芯和未掺杂或反掺杂外延壳的场效应晶体管（FET）器件的技术。一方面，提供一种制造FET器件的方法。该方法包括以下步骤。提供具有选自硅，硅锗和硅碳的半导体材料的晶片。在晶片中形成至少一个鳍芯。离子注入用于掺杂鳍芯。鳍芯的角部重新成形，使角落圆角或圆形。围绕鳍芯生长外延壳，其中外延壳包括选自硅，硅锗和硅碳的半导体材料。

84. 发明授权

US08536563B2 Nanowire field effect transistors 有权
标题翻译：纳米线场效应晶体管
公开(公告)号：US08536563B2
公开(公告)日：2013-09-17
申请号：US12884707
申请日：2010-09-17
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/4966 , H01L29/513 , H01L29/66439 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.
摘要翻译：一种用于形成纳米线场效应晶体管（FET）器件的方法，包括形成绝缘体上硅（SOI）焊盘区域，第二SOI焊盘区域，第三SOI焊盘区域，将第一SOI焊盘区域连接到第一SOI焊盘区域的第一SOI部分第二SOI焊盘区域和将第二SOI焊盘区域连接到衬底上的第三SOI焊盘区域的第二SOI部分，在第二SOI部分上形成第一硬掩模层，在半导体衬底上形成第一悬浮的纳米线，形成第一围绕第一悬浮纳米线的一部分构造栅极结构，在第一栅极结构和第一悬置纳米线上图案化第二硬掩模层，去除第一硬掩模层，在半导体衬底上形成第二悬浮纳米线，在第二栅极结构周围形成第二栅极结构第二悬浮纳米线的一部分，以及去除第二硬掩模层。

85. 发明授权

US08536041B2 Method for fabricating transistor with high-K dielectric sidewall spacer 有权
标题翻译：用于制造具有高K电介质侧壁间隔物的晶体管的方法
公开(公告)号：US08536041B2
公开(公告)日：2013-09-17
申请号：US13559182
申请日：2012-07-26
申请人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L27/01
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823462 , H01L21/823468 , H01L21/823807 , H01L21/823857 , H01L21/823864 , H01L27/1203 , H01L29/4958 , H01L29/517 , H01L29/66772 , H01L29/78654
摘要： A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.
摘要翻译：提供了一种用于制造晶体管的方法。该晶体管包括一个硅层，该硅层包括一个源区和一个漏极区，一个位于源极区和漏极区之间的硅层上的栅极堆叠，以及设置在栅叠层的侧壁上的侧壁隔离层。栅堆叠包括第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。侧壁间隔件包括高介电常数材料并且覆盖至少栅极叠层的第二和第三层的侧壁。还提供了制造这种晶体管的方法。

86. 发明申请

US20130176771A1 8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES 有权
标题翻译：具有外部门极二极管的8晶体管SRAM单元设计
公开(公告)号：US20130176771A1
公开(公告)日：2013-07-11
申请号：US13345636
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/40
CPC分类号： G11C16/24 , G11C11/412 , H01L27/0207 , H01L27/1104 , H01L27/1116
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
摘要翻译：一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到通过栅极和写入位之间的串联外部二极管的写入位线的每个通过栅极晶体管的源极或漏极线路阻止从写入位线进入电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

87. 发明申请

US20130175597A1 NANOWIRE FLOATING GATE TRANSISTOR 有权
标题翻译： NANOWIRE浮动门极晶体管
公开(公告)号：US20130175597A1
公开(公告)日：2013-07-11
申请号：US13344517
申请日：2012-01-05
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： G11C11/5671 , H01L21/28273 , H01L29/0673 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.
摘要翻译：浮栅晶体管，存储单元及其制造方法。浮栅晶体管包括一个或多个基本上圆柱形的选通线。浮置栅极晶体管包括至少部分地覆盖选通导线的第一栅极电介质层。浮置栅极晶体管还包括不连续地布置在第一栅极介电层上的多个栅极晶体。浮栅晶体管还包括覆盖多个栅极晶体和第一栅极介电层的第二栅极电介质层。

88. 发明申请

US20130153996A1 HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE 有权
标题翻译： HYBRID CMOS NANOWIRE MESH DEVICE和PDSOI DEVICE
公开(公告)号：US20130153996A1
公开(公告)日：2013-06-20
申请号：US13328069
申请日：2011-12-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/088 , H01L21/28 , H01L29/78 , B82Y40/00 , B82Y99/00
CPC分类号： H01L27/1203 , B82Y10/00 , B82Y40/00 , H01L21/28 , H01L21/845 , H01L27/088 , H01L27/1211 , H01L29/0673 , H01L29/66439 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.
摘要翻译：一种在SOI衬底上形成混合半导体结构的方法。该方法包括在同一SOI衬底上形成纳米线网状器件和PDSOI器件的集成工艺流程。还包括在同一SOI衬底上包括纳米线网状器件和PDSOI器件的半导体结构。

89. 发明授权

US08445337B2 Generation of multiple diameter nanowire field effect transistors 有权
标题翻译：生成多直径纳米线场效应晶体管
公开(公告)号：US08445337B2
公开(公告)日：2013-05-21
申请号：US12778517
申请日：2010-05-12
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L29/0669 , B82Y10/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions.
摘要翻译：提供了一种修改具有设置在绝缘体上的半导体的晶片的方法，包括以不同的初始半导体厚度建立晶片的第一和第二区域，形成经由每个第一和第二区域上的相应纳米线通道连接的半导体焊盘对，并重塑纳米线通道进入纳米线，每个纳米线具有反映第一和第二区域中的每一个处的不同初始半导体厚度的各自不同的厚度。

90. 发明授权

US08441043B2 Maskless process for suspending and thinning nanowires 失效
标题翻译：用于悬浮和稀化纳米线的无掩模工艺
公开(公告)号：US08441043B2
公开(公告)日：2013-05-14
申请号：US13006833
申请日：2011-01-14
申请人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/02488 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02667 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/78696 , Y10S977/762
摘要： Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.
摘要翻译：提供了基于半导体的电子器件及其制造技术。在一个方面，提供了一种包括第一垫的装置; 第二焊盘和多个纳米线，其以形成在掩埋氧化物（BOX）层上的绝缘体上硅（SOI）层中的梯形结构连接第一焊盘和第二焊盘，该纳米线具有一个或多个维度由硅从纳米线重新分配到焊盘。该器件可以包括具有围绕纳米线的栅极的场效应晶体管（FET），其中纳米线的部分由FET的栅极沟道围绕，第一焊盘和纳米线的部分从邻近第一焊盘形成FET的源极区域，并且第二焊盘和从与第二焊盘相邻的栅极延伸出的纳米线的部分形成FET的漏极区域。

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