专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US08754497B2 Strained LDMOS and demos 有权
标题翻译：应变的LDMOS和演示
公开(公告)号：US08754497B2
公开(公告)日：2014-06-17
申请号：US12789040
申请日：2010-05-27
申请人： Marie Denison , Seetharaman Sridhar , Sameer Pendharkar , Umamaheswari Aghoram
发明人： Marie Denison , Seetharaman Sridhar , Sameer Pendharkar , Umamaheswari Aghoram
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0692 , H01L29/7846
摘要： An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.
摘要翻译：在（100）衬底上的集成电路，其包含具有在<100>方向上取向的漂移区电流的n沟道扩展漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。应力源RESURF沟槽具有超过100 MPa压应力的应力元件。（100）衬底上的集成电路，其包含n沟道延伸漏极MOS晶体管，其漂移区电流以<110>方向取向，在漂移区中具有应力RESURF沟槽。应力源RESURF沟槽具有超过100 MPa压应力的应力元件。（100）衬底上的集成电路，其包含具有沿着<110>方向取向的漂移区电流的p沟道延伸漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。应力源RESURF沟槽具有超过100 MPa拉伸应力的应力元件。

82. 发明授权

US08399924B2 High voltage transistor using diluted drain 有权
公开(公告)号：US08399924B2
公开(公告)日：2013-03-19
申请号：US13160759
申请日：2011-06-15
申请人： Pinghai Hao , Sameer Pendharkar , Binghua Hu , Qingfeng Wang
发明人： Pinghai Hao , Sameer Pendharkar , Binghua Hu , Qingfeng Wang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0847 , H01L21/266 , H01L21/823412 , H01L21/823418 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/66659 , H01L29/7835
摘要： An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

83. 发明申请

US20110309440A1 HIGH VOLTAGE TRANSISTOR USING DILUTED DRAIN 有权
标题翻译：使用稀释漏水的高压晶体管
公开(公告)号：US20110309440A1
公开(公告)日：2011-12-22
申请号：US13160759
申请日：2011-06-15
申请人： Pinghai Hao , Sameer Pendharkar , Binghua Hu , Qingfeng Wang
发明人： Pinghai Hao , Sameer Pendharkar , Binghua Hu , Qingfeng Wang
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/0847 , H01L21/266 , H01L21/823412 , H01L21/823418 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/66659 , H01L29/7835
摘要： An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.
摘要翻译：包含扩展漏极MOS晶体管的集成电路可以通过形成具有掩模手指的沟道区域的漂移区域注入掩模来形成，并且延伸到源极/沟道有源区，但不延伸到漏极接触有源区。通过暴露的指状物注入的掺杂剂在掩模指下面的衬底中形成横向掺杂条纹。栅极下方的漂移区域的平均掺杂密度比漏极接触有效面积处的漂移区域的平均掺杂密度小至少25％。在一个实施例中，掺杂剂横向漫射以形成连续漂移区域。在另一个实施例中，横向掺杂条纹之间的衬底材料与横向掺杂条纹保持相反的导电类型。

84. 发明授权

US07847351B2 Lateral metal oxide semiconductor drain extension design 有权
标题翻译：横向金属氧化物半导体漏极扩展设计
公开(公告)号：US07847351B2
公开(公告)日：2010-12-07
申请号：US12101608
申请日：2008-04-11
申请人： Marie Denison , Seetharaman Sridhar , Sameer Pendharkar
发明人： Marie Denison , Seetharaman Sridhar , Sameer Pendharkar
IPC分类号： H01L29/76
CPC分类号： H01L29/402 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes.
摘要翻译：一种包括源极和漏极区域以及绝缘区域和板状结构的半导体器件。源区和漏区在半导体衬底上或半导体衬底中。绝缘区域位于或位于半导体衬底中并位于源区和漏区之间。绝缘区域具有薄层和厚层。厚层包括彼此分离并且跨越源极和漏极区域之间的长度延伸的多个绝缘条。板结构位于源区和漏区之间，其中板结构位于薄层和厚层的部分上，板结构具有一个或多个导电带，其直接位于多个绝缘中的单独绝缘层上条纹。

85. 发明申请

US20100163998A1 TRENCH ISOLATION COMPRISING PROCESS HAVING MULTIPLE GATE DIELECTRIC THICKNESSES AND INTEGRATED CIRCUITS THEREFROM 有权
标题翻译：具有多个栅极介质厚度的封装隔离工艺及其集成电路
公开(公告)号：US20100163998A1
公开(公告)日：2010-07-01
申请号：US12345072
申请日：2008-12-29
申请人： Seetharaman Sridhar , Sameer Pendharkar , Dan M. Mosher
发明人： Seetharaman Sridhar , Sameer Pendharkar , Dan M. Mosher
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L21/823462 , H01L21/76229 , H01L21/823481 , H01L21/823857 , H01L21/823878
摘要： A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness
摘要翻译：一种制造集成电路（IC）的方法，所述集成电路（IC）包括第一多个MOS晶体管，所述第一多个MOS晶体管具有在第一区域中具有第一厚度的第一栅极电介质，以及第二多个MOS晶体管，其中所述第一厚度<所述第二厚度。提供具有半导体表面的衬底。具有厚度为nlE的焊盘电介质层;在包括第二区域的半导体表面上形成第二厚度，其中焊盘介电层为第二栅极电介质提供第二厚度的至少一部分。在包括第二区域的半导体表面上形成硬掩模层。通过蚀刻通过焊盘介电层和半导体表面的一部分形成多个沟槽隔离区域。多个沟槽隔离区域填充有介电填充材料以形成沟槽隔离区域，然后去除硬掩模层。在第二栅极电介质上形成图案化的栅极电极层，其中所述图案化的栅极电极层在至少一个沟槽隔离区域的表面上延伸。然后完成第一和第二区域中的MOS晶体管的制造。

86. 发明申请

US20090256199A1 LATERAL METAL OXIDE SEMICONDUCTOR DRAIN EXTENSION DESIGN 有权
标题翻译：侧向金属氧化物半导体漏斗扩展设计
公开(公告)号：US20090256199A1
公开(公告)日：2009-10-15
申请号：US12101608
申请日：2008-04-11
申请人： Marie Denison , Seetharaman Sridhar , Sameer Pendharkar
发明人： Marie Denison , Seetharaman Sridhar , Sameer Pendharkar
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L29/402 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes.
摘要翻译：一种包括源极和漏极区域以及绝缘区域和板状结构的半导体器件。源区和漏区在半导体衬底上或半导体衬底中。绝缘区域位于或位于半导体衬底中并位于源区和漏区之间。绝缘区域具有薄层和厚层。厚层包括彼此分离并且跨越源极和漏极区域之间的长度延伸的多个绝缘条。板结构位于源区和漏区之间，其中板结构位于薄层和厚层的部分上，板结构具有一个或多个导电带，其直接位于多个绝缘中的单独绝缘层上条纹。

87. 发明申请

US20080246117A1 SURFACE PATTERNED TOPOGRAPHY FEATURE SUITABLE FOR PLANARIZATION 有权
标题翻译：表面图案特征适用于平面化
公开(公告)号：US20080246117A1
公开(公告)日：2008-10-09
申请号：US11696829
申请日：2007-04-05
申请人： Sameer Pendharkar , Binghua Hu , Xinfen Celia Chen
发明人： Sameer Pendharkar , Binghua Hu , Xinfen Celia Chen
IPC分类号： H01L21/4763 , H01L21/04 , H01L29/72
CPC分类号： H01L29/7322 , H01L23/544 , H01L29/41708 , H01L29/66272 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.
摘要翻译：一种用于制造半导体器件的方法，包括在衬底的阱区中注入第一掺杂剂类型以形成由所述阱区的非植入区域分离的注入的子区。该方法还包括在阱区上形成氧化物层，使得注入的子区域的氧化物转化的第一厚度大于非植入区域的氧化物转化的第二厚度。该方法还包括去除氧化物层以在阱区上形成形貌特征。地形特征包括较高和较低部分的表面图案。更高的部分对应于非植入区域的位置，并且下部对应于植入的子区域。

88. 发明授权

US07238986B2 Robust DEMOS transistors and method for making the same 有权
标题翻译：坚固的DEMOS晶体管及其制造方法
公开(公告)号：US07238986B2
公开(公告)日：2007-07-03
申请号：US10837918
申请日：2004-05-03
申请人： Sameer Pendharkar , Ramanathan Ramani , Taylor R. Efland
发明人： Sameer Pendharkar , Ramanathan Ramani , Taylor R. Efland
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.
摘要翻译：提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有第一种掺杂剂的浓度高于第二部分。

89. 发明授权

US07176091B2 Drain-extended MOS transistors and methods for making the same 有权
标题翻译：漏极扩散MOS晶体管及其制造方法
公开(公告)号：US07176091B2
公开(公告)日：2007-02-13
申请号：US11082166
申请日：2005-03-16
申请人： Sameer Pendharkar
发明人： Sameer Pendharkar
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L29/1083 , H01L29/42368 , H01L29/66689
摘要： Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).
摘要翻译：描述了漏极扩散MOS晶体管（T 1，T 2）和半导体器件（102）及其制造方法（202），其中在形成外延硅之前形成p埋层（130） 106），并且在外延硅层（106）中形成漏极扩展MOS晶体管（T 1，T 2）。 p埋层（130）可以形成在用于高侧驱动晶体管（T 2）应用的衬底（104）中的n掩埋层（120）上方，其中p埋层（130）在漏极扩展MOS晶体管（T 2）和n掩埋层（120），以抑制源极（154）和漏极（156）之间的截止状态击穿。

90. 发明申请

US20060170056A1 Drain extended PMOS transistor with increased breakdown voltage 有权
标题翻译：以增加的击穿电压漏极扩展PMOS晶体管
公开(公告)号：US20060170056A1
公开(公告)日：2006-08-03
申请号：US11047418
申请日：2005-01-31
申请人： Shanjen Pan , Sameer Pendharkar , James Todd
发明人： Shanjen Pan , Sameer Pendharkar , James Todd
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of the p-type upper epitaxial layer (106) is sandwiched between a left P-WELL region (130a) and a right P-WELL region (130b) formed within the p-type upper epitaxial layer (106). The p-type upper epitaxial layer (106) is formed over a semiconductor body (104) that has an n-buried layer (108) formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended PMOS transistor.
摘要翻译：提供了包括漏极延伸PMOS晶体管（CT1a）的半导体器件（102），以及制造方法（202）。在形成PMOS晶体管时，晶体管的漏极（124）形成在p型上部外延层（106）的区域（125）上，其中p型上部外延层（106）的区域（125））夹在形成在p型上部外延层（106）内的左P-WELL区域（130a）和右P-WELL区域（130b）之间。 p型上部外延层（106）形成在其上形成有n埋层（108）的半导体本体（104）上。这种布置用于增加漏极延伸PMOS晶体管的击穿电压（BVdss）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式