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81. 发明申请

US20120138888A1 Single Gate Inverter Nanowire Mesh 失效
标题翻译：单门逆变器纳米线网
公开(公告)号：US20120138888A1
公开(公告)日：2012-06-07
申请号：US13316515
申请日：2011-12-11
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L27/088 , H01L29/775 , B82Y99/00
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译：提供一种FET逆变器，其包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和多个纳米线通道，其中一个或多个器件层的源极和漏极区掺杂有n型掺杂剂，并且一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。还提供了用于制造FET逆变器的技术。

82. 发明申请

US20100295021A1 Single Gate Inverter Nanowire Mesh 有权
标题翻译：单门逆变器纳米线网
公开(公告)号：US20100295021A1
公开(公告)日：2010-11-25
申请号：US12470128
申请日：2009-05-21
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L29/15 , H01L21/336 , H01L27/12
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译：提供基于纳米线的设备。一方面，提供了场效应晶体管（FET）逆变器。 FET反相器包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个更多的器件层掺杂有n型掺杂剂，并且器件层中的一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。还提供了用于制造FET逆变器的技术。

83. 发明授权

US08472239B2 Nanowire mesh FET with multiple threshold voltages 失效
公开(公告)号：US08472239B2
公开(公告)日：2013-06-25
申请号：US13467126
申请日：2012-05-09
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： G11C11/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

84. 发明授权

US08395220B2 Nanomesh SRAM cell 有权
标题翻译： Nanomesh SRAM单元
公开(公告)号：US08395220B2
公开(公告)日：2013-03-12
申请号：US13417829
申请日：2012-03-12
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L27/088 , B82Y99/00
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L27/0688 , H01L27/11 , H01L27/1104 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.
摘要翻译：提供基于纳米线的设备。在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。

85. 发明申请

US20120217479A1 Nanowire Mesh FET with Multiple Threshold Voltages 失效
标题翻译：具有多个阈值电压的纳米线网状FET
公开(公告)号：US20120217479A1
公开(公告)日：2012-08-30
申请号：US13467126
申请日：2012-05-09
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
摘要翻译：提供了基于纳米线的场效应晶体管（FET）及其制造技术。在一个方面，提供了一种FET，其具有在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个的器件层被配置为具有来自一个或多个其它器件层的不同阈值电压; 以及围绕纳米线通道的每个器件层共用的栅极。

86. 发明授权

US08916054B2 High fidelity patterning employing a fluorohydrocarbon-containing polymer 有权
标题翻译：采用含氟代烃基聚合物的高保真图案
公开(公告)号：US08916054B2
公开(公告)日：2014-12-23
申请号：US13281749
申请日：2011-10-26
申请人： Markus Brink , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Hiroyuki Miyazoe , Masahiro Nakamura
发明人： Markus Brink , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Hiroyuki Miyazoe , Masahiro Nakamura
IPC分类号： B44C1/22 , H01L21/033 , H01L21/311 , G03F7/40 , G03F7/09
CPC分类号： G03F7/094 , G03F7/091 , G03F7/40 , H01L21/0332 , H01L21/31116 , H01L21/31122 , H01L21/31138 , H01L21/31144 , Y10T428/24479
摘要： A stack of a hard mask layer, a soft mask layer, and a photoresist is formed on a substrate. The photoresist is patterned to include at least one opening. The pattern is transferred into the soft mask layer by an anisotropic etch, which forms a carbon-rich polymer that includes more carbon than fluorine. The carbon-rich polymer can be formed by employing a fluorohydrocarbon-containing plasma generated with fluorohydrocarbon molecules including more hydrogen than fluorine. The carbon-rich polymer coats the sidewalls of the soft mask layer, and prevents widening of the pattern transferred into the soft mask. The photoresist is subsequently removed, and the pattern in the soft mask layer is transferred into the hard mask layer. Sidewalls of the hard mask layer are coated with the carbon-rich polymer to prevent widening of the pattern transferred into the hard mask.
摘要翻译：在基板上形成硬掩模层，软掩模层和光致抗蚀剂的堆叠。图案化光致抗蚀剂以包括至少一个开口。该图案通过各向异性蚀刻转移到软掩模层中，其形成包含比氟更多的碳的富碳聚合物。富含碳的聚合物可以通过使用包含比氟更多的氢的氟代烃分子产生的含氟代烃等离子体形成。富含碳的聚合物涂覆软掩模层的侧壁，并且防止转移到软掩模中的图案的加宽。随后去除光致抗蚀剂，并将软掩模层中的图案转移到硬掩模层中。用富含碳的聚合物涂覆硬掩模层的侧壁以防止转移到硬掩模中的图案变宽。

87. 发明申请

US20140014904A1 Replacement Contacts for All-Around Contacts 有权
标题翻译：全方位联系人的替换联系人
公开(公告)号：US20140014904A1
公开(公告)日：2014-01-16
申请号：US13558532
申请日：2012-07-26
申请人： Guy M. Cohen , Michael A. Guillorn
发明人： Guy M. Cohen , Michael A. Guillorn
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/413 , H01L29/42364 , H01L29/66439
摘要： In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device.
摘要翻译：一方面，提供一种FET器件。 FET器件包括衬底; 衬底上的半导体材料; 所述衬底上的至少一个栅极围绕用作所述器件的沟道区的所述半导体材料的一部分，其中从所述栅极延伸的所述半导体材料的部分用作所述器件的源极和漏极区域，并且其中所述源极和器件的漏极区域从衬底移位; 覆盖栅极和半导体材料的器件上的平坦化电介质; 以及延伸穿过平坦化电介质并且围绕器件的源极和漏极区域的触点。

88. 发明授权

US08586455B1 Preventing shorting of adjacent devices 失效
标题翻译：防止相邻设备短路
公开(公告)号：US08586455B1
公开(公告)日：2013-11-19
申请号：US13471487
申请日：2012-05-15
申请人： Josephine Chang , Michael A. Guillorn , Balasubramanian Pranatharthiharan , Jeffrey William Sleight
发明人： Josephine Chang , Michael A. Guillorn , Balasubramanian Pranatharthiharan , Jeffrey William Sleight
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/76202 , H01L21/823431 , H01L21/845 , H01L27/1104 , H01L27/1108
摘要： Embodiments of the present invention provide a method of preventing electrical shorting of adjacent semiconductor devices. The method includes forming a plurality of fins of a plurality of field-effect-transistors on a substrate; forming at least one barrier structure between a first and a second fin of the plurality of fins; and growing an epitaxial film from the plurality of fins, the epitaxial film extending horizontally from sidewalls of at least the first and second fins and reaching the barrier structure situating between the first and second fins.
摘要翻译：本发明的实施例提供一种防止相邻半导体器件的电短路的方法。该方法包括在衬底上形成多个场效应晶体管的多个散热片; 在所述多个翅片的第一和第二翅片之间形成至少一个阻挡结构; 以及从所述多个翅片生长外延膜，所述外延膜从至少所述第一和第二鳍片的侧壁水平延伸并到达位于所述第一和第二鳍片之间的所述阻挡结构。

89. 发明授权

US08492208B1 Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process 有权
标题翻译：用替代栅极工艺制造的纳米线FET中的压电（PFET）和拉伸（NFET）沟道应变
公开(公告)号：US08492208B1
公开(公告)日：2013-07-23
申请号：US13344352
申请日：2012-01-05
申请人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
发明人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
IPC分类号： H01L21/00 , H01L29/76
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/66439
摘要： A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
摘要翻译：提供一种制造FET器件的方法，其包括以下步骤。纳米线/焊盘形成在BOX层上的SOI层中，其中纳米线悬挂在BOX上。沉积围绕纳米线的HSQ层。围绕纳米线的HSQ层的一部分交联，其中交联导致HSQ层的一部分收缩，从而诱导纳米线中的应变。形成一个或多个保持在纳米线中诱发的应变的栅极。还提供了一种FET器件，其中每个纳米线具有变形的第一区域，使得第一区域中的晶格常数小于纳米线的松弛晶格常数和第二区域，其变形使得第二区域中的晶格常数大于纳米线的松弛晶格常数。

90. 发明申请

US20130020183A1 Silicide Micromechanical Device and Methods to Fabricate Same 有权
标题翻译：硅化物微机械装置及其制造方法
公开(公告)号：US20130020183A1
公开(公告)日：2013-01-24
申请号：US13625294
申请日：2012-09-24
申请人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
发明人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
IPC分类号： H01H59/00
CPC分类号： B81C1/00666 , B81C1/00952 , H01H1/0094 , H01H2001/0078
摘要： A miniaturized electro-mechanical switch includes a moveable portion having a contact configured to make, when the switch is actuated, an electrical connection between two stationary points. At least the contact is composed of a fully silicided material. A structure includes a silicon layer formed over an insulator layer and a micromechanical switch formed at least partially within the silicon layer. The micromechanical switch has a conductive structure, and where at least electrically contacting portions of the conductive structure are comprised of fully silicided material.
摘要翻译：小型化机电开关包括具有触点的可移动部分，该触点构造成当开关被致动时使得两个静止点之间的电连接。至少接触由完全硅化的材料组成。一种结构包括形成在绝缘体层上的硅层和至少部分地形成在硅层内的微机电开关。微机械开关具有导电结构，并且其中导电结构的至少电接触部分由完全硅化材料构成。

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