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81. 发明授权

US08364900B2 Pseudo-LRU cache line replacement for a high-speed cache 有权
标题翻译：用于高速缓存的伪LRU高速缓存行替代
公开(公告)号：US08364900B2
公开(公告)日：2013-01-29
申请号：US12029889
申请日：2008-02-12
申请人： Paul Caprioli , Sherman H. Yip , Shailender Chaudhry
发明人： Paul Caprioli , Sherman H. Yip , Shailender Chaudhry
IPC分类号： G06F12/00
CPC分类号： G06F12/125 , G06F12/0864 , Y02D10/13
摘要： Embodiments of the present invention provide a system that replaces an entry in a least-recently-used way in a skewed-associative cache. The system starts by receiving a cache line address. The system then generates two or more indices using the cache line address. Next, the system generates two or more intermediate indices using the two or more indices. The system then uses at least one of the two or more indices or the two or more intermediate indices to perform a lookup in one or more lookup tables, wherein the lookup returns a value which identifies a least-recently-used way. Next, the system replaces the entry in the least-recently-used way.
摘要翻译：本发明的实施例提供了一种在偏斜相关高速缓存中以最近最近使用的方式替换条目的系统。系统从接收缓存行地址开始。然后系统使用高速缓存行地址生成两个或多个索引。接下来，系统使用两个或更多个索引生成两个或更多个中间索引。然后，系统使用两个或更多个索引中的至少一个或两个或更多个中间索引来在一个或多个查找表中执行查找，其中查找返回标识最近最近使用的方式的值。接下来，系统以最近最少使用的方式替换条目。

82. 发明申请

US20120166756A1 INDEX GENERATION FOR CACHE MEMORIES 有权
标题翻译：高速缓存记录的索引生成
公开(公告)号：US20120166756A1
公开(公告)日：2012-06-28
申请号：US13402796
申请日：2012-02-22
申请人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
发明人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
摘要翻译：本发明的实施例提供一种生成高速缓冲存储器的索引的系统。系统通过接收访问高速缓冲存储器的请求开始，其中请求包括地址信息。然后系统获得与请求相关联的非地址信息。接下来，系统使用地址信息和非地址信息来生成索引。然后，系统使用索引来实现对高速缓存的访问。

83. 发明授权

US07930695B2 Method and apparatus for synchronizing threads on a processor that supports transactional memory 有权
标题翻译：用于在支持事务性存储器的处理器上同步线程的方法和装置
公开(公告)号：US07930695B2
公开(公告)日：2011-04-19
申请号：US11418652
申请日：2006-05-05
申请人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
发明人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3857
摘要： One embodiment of the present invention provides a system that synchronizes threads on a multi-threaded processor. The system starts by executing instructions from a multi-threaded program using a first thread and a second thread. When the first thread reaches a predetermined location in the multi-threaded program, the first thread executes a Start-Transactional-Execution (STE) instruction to commence transactional execution, wherein the STE instruction specifies a location to branch to if transactional execution fails. During the subsequent transactional execution, the first thread accesses a mailbox location in memory (which is also accessible by the second thread) and then executes instructions that cause the first thread to wait. When the second thread reaches a second predetermined location in the multi-threaded program, the second thread signals the first thread by accessing the mailbox location, which causes the transactional execution of the first thread to fail, thereby causing the first thread to resume non-transactional execution from the location specified in the STE instruction. In this way, the second thread can signal to the first thread without the first thread having to poll a shared variable.
摘要翻译：本发明的一个实施例提供了一种在多线程处理器上同步线程的系统。系统通过使用第一个线程和第二个线程执行来自多线程程序的指令来启动。当第一线程到达多线程程序中的预定位置时，第一线程执行开始 - 事务执行（STE）指令以开始事务执行，其中STE指令指定分支到事务执行失败的位置。在随后的事务执行期间，第一个线程访问存储器中的邮箱位置（也可由第二个线程访问），然后执行使第一个线程等待的指令。当第二线程到达多线程程序中的第二预定位置时，第二线程通过访问邮箱位置来发信号通知第一线程，这导致第一线程的事务性执行失败，从而使第一线程恢复为非线程，从STE指令中指定的位置进行事务执行。以这种方式，第二线程可以向第一线程发信号，而第一线程不必轮询共享变量。

84. 发明授权

US07707359B2 Method and apparatus for selectively prefetching based on resource availability 有权
标题翻译：用于基于资源可用性选择性地预取的方法和装置
公开(公告)号：US07707359B2
公开(公告)日：2010-04-27
申请号：US11390896
申请日：2006-03-27
申请人： Wayne Mesard , Paul Caprioli
发明人： Wayne Mesard , Paul Caprioli
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F9/30047 , G06F9/30072 , G06F9/3802 , G06F9/383 , G06F2212/6028
摘要： One embodiment of the present invention provides a system which facilitates selective prefetching based on resource availability. During operation, the system executes instructions in a processor. While executing the instructions, the system monitors the availability of one or more system resources and dynamically adjusts an availability indicator for each system resource based on the current availability of the system resource. Upon encountering a prefetch instruction which involves the system resource, the system checks the availability indicator. If the availability indicator indicates that the system resource is not sufficiently available, the system terminates the execution of the prefetch instruction, whereby terminating execution prevents prefetch instructions from overwhelming the system resource.
摘要翻译：本发明的一个实施例提供一种基于资源可用性促进选择性预取的系统。在操作期间，系统在处理器中执行指令。在执行指令时，系统监视一个或多个系统资源的可用性，并根据系统资源的当前可用性动态调整每个系统资源的可用性指标。在遇到涉及系统资源的预取指令时，系统检查可用性指标。如果可用性指示符指示系统资源不够可用，则系统终止预取指令的执行，由此终止执行防止预取指令压倒系统资源。

85. 发明授权

US07634641B2 Method and apparatus for using multiple threads to spectulatively execute instructions 有权
标题翻译：使用多个线程来分析执行指令的方法和装置
公开(公告)号：US07634641B2
公开(公告)日：2009-12-15
申请号：US11361257
申请日：2006-04-24
申请人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
发明人： Shailender Chaudhry , Marc Tremblay , Paul Caprioli
IPC分类号： G06F9/00 , G06F9/40
CPC分类号： G06F9/3851 , G06F9/383 , G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system which performs simultaneous speculative threading. The system staffs by executing instructions in normal execution mode using a first thread. Upon encountering a data-dependent stall condition, the first thread generates an architectural checkpoint and commences execution of instructions in execute-ahead mode. During execute-ahead mode, the first thread executes instructions that can be executed and defers instructions that cannot be executed into a deferred queue. When the data dependent stall condition has been resolved, the first thread generates a speculative checkpoint and continues execution in execute-ahead mode. At the same time, the second thread commences execution in a deferred mode. During execution in the deferred mode, the second thread executes instructions deferred by the first thread.
摘要翻译：本发明的一个实施例提供一种执行同时投机线程的系统。系统通过使用第一个线程在正常执行模式下执行指令来启动。在遇到数据相关的停顿条件时，第一个线程生成架构检查点，并以执行提前模式开始执行指令。在执行提前模式期间，第一个线程执行可执行的指令，并将不能执行的指令拖到延迟队列中。当数据相关的停顿条件已经解决时，第一个线程生成一个推测性检查点，并以执行提前模式继续执行。同时，第二个线程以延迟模式开始执行。在延迟模式执行期间，第二线程执行由第一线程延迟的指令。

86. 发明申请

US20090300338A1 AGGRESSIVE STORE MERGING IN A PROCESSOR THAT SUPPORTS CHECKPOINTING 有权
标题翻译：在支持检查的处理器中进行积极的存储合并
公开(公告)号：US20090300338A1
公开(公告)日：2009-12-03
申请号：US12128332
申请日：2008-05-28
申请人： Paul Caprioli , Martin Karlsson , Gideon N. Levinsky , Khondakar A. Mujtaba , Shailender Chaudhry , Murali K. Inaganti
发明人： Paul Caprioli , Martin Karlsson , Gideon N. Levinsky , Khondakar A. Mujtaba , Shailender Chaudhry , Murali K. Inaganti
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3834 , G06F9/3863
摘要： Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging of stores into existing entries in the store queue. Then, upon detecting a predetermined condition, the processor is configured to generate a checkpoint. After generating the checkpoint, the processor is configured to continue to execute instructions. When executing instructions after the checkpoint is generated, the processor is configured to freely merge subsequent stores into post-checkpoint entries in the store queue.
摘要翻译：本发明的实施例提供了一种处理器，其将存储结合在N入口先进先出（FIFO）存储队列中。在这些实施例中，处理器通过在生成检查点之前执行指令来开始。在生成检查点之前执行指令时，处理器被配置为对存储队列中的现有条目执行有限或不合并存储。然后，在检测到预定条件时，处理器被配置为生成检查点。生成检查点后，处理器配置为继续执行指令。在检查点生成后执行指令时，处理器被配置为将后续存储自由合并到存储队列中的后检查点条目中。

87. 发明申请

US20090187906A1 SEMI-ORDERED TRANSACTIONS 审中-公开
标题翻译：半订单交易
公开(公告)号：US20090187906A1
公开(公告)日：2009-07-23
申请号：US12018417
申请日：2008-01-23
申请人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
发明人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
IPC分类号： G06F9/46
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3851 , G06F9/3863
摘要： Embodiments of the present invention provide a system that facilitates transactional execution in a processor. The system starts by executing program code for a thread in a processor. Upon detecting a predetermined indicator, the system starts a transaction for a section of the program code for the thread. When starting the transaction, the system executes a checkpoint instruction. If the checkpoint instruction is a WEAK_CHECKPOINT instruction, the system executes a semi-ordered transaction. During the semi-ordered transaction, the system preserves code atomicity but not memory atomicity. Otherwise, the system executes a regular transaction. During the regular transaction, the system preserves both code atomicity and memory atomicity.
摘要翻译：本发明的实施例提供一种促进处理器中的事务执行的系统。系统通过为处理器中的线程执行程序代码来启动。在检测到预定指示符时，系统针对线程的程序代码的一部分开始事务。开始事务时，系统执行检查点指令。如果检查点指令是WEAK_CHECKPOINT指令，则系统执行半订单事务。在半订单事务期间，系统保留代码原子性，但不保留内存原子性。否则，系统将执行常规事务。在常规事务期间，系统保留代码原子性和内存原子性。

88. 发明授权

US07509481B2 Patchable and/or programmable pre-decode 有权
标题翻译：可修补和/或可编程预解码
公开(公告)号：US07509481B2
公开(公告)日：2009-03-24
申请号：US11277735
申请日：2006-03-28
申请人： Shailender Chaudhry , Paul Caprioli , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F9/00
CPC分类号： G06F9/30145 , G06F9/30174 , G06F9/30196 , G06F9/382 , G06F9/3822 , G06F9/3897
摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue. In some realizations, operation of pre-decode may be reprogrammed post-manufacture, at (or about) initialization, or at run-time.
摘要翻译：已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。特别地，已经发现可以采用可编程预解码机制来改变处理器的行为。例如，用于排序，同步或推测控制的预解码提示可以改变或者将ISA指令映射到本地指令或操作序列可以被改变。可以采用这样的技术来使处理器实现（在现场中）适应于变化的存储器模型，实现或接口或者改变存储器延迟或定时特性。类似地，可以采用这样的技术来使处理器实现适应于扩展/适应的指令集架构。在一些实现中，可以在处理器运行时调整指令预解码功能以处理或减轻定时，并发或推测问题。在某些实现中，可以在（或大约）初始化或运行时在制造后重新编程预解码的操作。

89. 发明授权

US07509472B2 Collapsible front-end translation for instruction fetch 有权
标题翻译：可折叠的前端翻译用于指令提取
公开(公告)号：US07509472B2
公开(公告)日：2009-03-24
申请号：US11345165
申请日：2006-02-01
申请人： Paul Caprioli , Shailender Chaudhry
发明人： Paul Caprioli , Shailender Chaudhry
IPC分类号： G06F9/26 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3804 , G06F9/30054 , G06F12/0875 , G06F12/10 , G06F2212/655 , Y02D10/13
摘要： Address translation for instruction fetching can be obviated for sequences of instruction instances that reside on a same page. Obviating address translation reduces power consumption and increases pipeline efficiency since accessing of an address translation buffer can be avoided. Certain events, such as branch mis-predictions and exceptions, can be designated as page boundary crossing events. In addition, carry over at a particular bit position when computing a branch target or a next instruction instance fetch target can also be designated as a page boundary crossing event. An address translation buffer is accessed to translate an address representation of a first instruction instance. However, until a page boundary crossing event occurs, the address representations of subsequent instruction instances are not translated. Instead, the translated portion of the address representation for the first instruction instance is recycled for the subsequent instruction instances.
摘要翻译：针对驻留在同一页面上的指令实例的序列，可以避免用于指令获取的地址转换。避免访问地址转换缓冲区，避免地址转换降低功耗并提高管道效率。某些事件，如分支错误预测和例外，可以被指定为页边界交叉事件。此外，当计算分支目标或下一指令实例提取目标时，在特定比特位置进位也可以被指定为页边界交叉事件。访问地址转换缓冲器以转换第一指令实例的地址表示。然而，直到发生页边界交叉事件，后续指令实例的地址表示不被转换。相反，第一个指令实例的地址表示的翻译部分被回收用于后续指令实例。

90. 发明授权

US07418581B2 Method and apparatus for sampling instructions on a processor that supports speculative execution 有权
标题翻译：用于在支持推测性执行的处理器上对指令进行采样的方法和装置
公开(公告)号：US07418581B2
公开(公告)日：2008-08-26
申请号：US11405965
申请日：2006-04-17
申请人： Shailender Chaudhry , Paul Caprioli , Sherman H. Yip
发明人： Shailender Chaudhry , Paul Caprioli , Sherman H. Yip
IPC分类号： G06F9/30
CPC分类号： G06F11/3466 , G06F9/3842 , G06F9/3867
摘要： One embodiment of the present invention provides a system that samples instructions on a processor that supports speculative-execution. The system starts by selecting an instruction, wherein selecting an instruction involves selecting an instruction that is received from an instruction fetch unit or a deferred queue, wherein the deferred queue holds deferred instructions which are deferred because of an unresolved data dependency. The system then records information about the selected instruction during execution of the selected instruction, whereby the recorded information can be used to determine the performance of the processor.
摘要翻译：本发明的一个实施例提供了一种在支持推测执行的处理器上对指令进行采样的系统。系统首先选择指令，其中选择指令涉及选择从指令获取单元或延迟队列接收的指令，其中延迟队列保存由于未解决的数据依赖性而延迟的延迟指令。然后，系统在执行所选择的指令期间记录关于所选指令的信息，由此可以使用所记录的信息来确定处理器的性能。

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