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81. 发明申请

US20080261370A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080261370A1
公开(公告)日：2008-10-23
申请号：US12155272
申请日：2008-06-02
申请人： Isao Kamioka , Yoshio Ozawa
发明人： Isao Kamioka , Yoshio Ozawa
IPC分类号： H01L21/336
CPC分类号： H01L29/40114 , H01L21/3247 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a first conductive layer on the first insulating film; forming a second insulating film on the first conductive layer in a first processing chamber isolated from an outside; performing a modification process on the second insulating film in the first processing chamber, and unloading the semiconductor substrate from the first processing chamber to the outside; annealing the second insulating film in a second processing chamber; and forming a second conductive layer on the second insulating film.
摘要翻译：根据本发明，提供一种半导体器件制造方法，包括：在半导体衬底上形成第一绝缘膜; 在所述第一绝缘膜上形成第一导电层; 在与外部隔离的第一处理室中在所述第一导电层上形成第二绝缘膜; 对第一处理室中的第二绝缘膜执行修改处理，并将半导体衬底从第一处理室卸载到外部; 在第二处理室中退火第二绝缘膜; 以及在所述第二绝缘膜上形成第二导电层。

82. 发明授权

US07396721B2 Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07396721B2
公开(公告)日：2008-07-08
申请号：US11130128
申请日：2005-05-17
申请人： Isao Kamioka , Yoshio Ozawa
发明人： Isao Kamioka , Yoshio Ozawa
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/3247 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a first conductive layer on the first insulating film; forming a second insulating film on the first conductive layer in a first processing chamber isolated from an outside; performing a modification process on the second insulating film in the first processing chamber, and unloading the semiconductor substrate from the first processing chamber to the outside; annealing the second insulating film in a second processing chamber; and forming a second conductive layer on the second insulating film.
摘要翻译：根据本发明，提供一种半导体器件制造方法，包括：在半导体衬底上形成第一绝缘膜; 在所述第一绝缘膜上形成第一导电层; 在与外部隔离的第一处理室中在所述第一导电层上形成第二绝缘膜; 对第一处理室中的第二绝缘膜执行修改处理，并将半导体衬底从第一处理室卸载到外部; 在第二处理室中退火第二绝缘膜; 以及在所述第二绝缘膜上形成第二导电层。

83. 发明申请

US20080149932A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080149932A1
公开(公告)日：2008-06-26
申请号：US11946606
申请日：2007-11-28
申请人： Katsuaki Natori , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka , Masayuki Tanaka , Kazuaki Nakajima , Yoshio Ozawa , Akihito Yamamoto
发明人： Katsuaki Natori , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka , Masayuki Tanaka , Kazuaki Nakajima , Yoshio Ozawa , Akihito Yamamoto
IPC分类号： H01L27/115
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/513 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control electrode containing metal or metal silicide provided on the charge storage layer via the second insulating film, wherein a corner of a lower part of the control electrode includes semiconductor and fails to contain the metal or the metal silicide in a channel width direction view of the memory cell.
摘要翻译：半导体器件包括半导体衬底和设置在半导体衬底上并且包括布置在半导体衬底上的多个存储单元的存储单元阵列，多个存储单元中的每一个包括设置在半导体衬底上的第一绝缘膜，设置在所述第一绝缘膜上的电荷存储层，设置在所述电荷存储层上的第二绝缘膜，以及经由所述第二绝缘膜设置在所述电荷存储层上的含有金属或金属硅化物的控制电极，的控制电极包括半导体，并且在存储单元的沟道宽度方向视图中不能容纳金属或金属硅化物。

84. 发明授权

US07391076B2 Non-volatile memory cells 有权
标题翻译：非易失性存储单元
公开(公告)号：US07391076B2
公开(公告)日：2008-06-24
申请号：US11709160
申请日：2007-02-22
申请人： Yoshio Ozawa
发明人： Yoshio Ozawa
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/42336 , H01L29/7883
摘要： A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof, a control gate electrode above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.
摘要翻译：半导体器件包括半导体衬底和设置在半导体衬底上的非易失性存储单元，所述非易失性存储单元包括设置在半导体衬底上的隧道绝缘膜，设置在隧道绝缘膜上的浮置栅电极，所述浮栅电极的宽度在所述非易失性存储单元的沟道宽度或长度方向上在高度方向上变化，并且在所述浮栅电极的底表面之上的区域和其上表面之下的区域中最薄，设置在所述控制栅电极和所述浮置栅电极之间的电极间绝缘膜。

85. 发明申请

US20080102616A1 Semiconductor device having a gate insulating film structure including an insulating film containing metal, silicon and oxygen and manufacturing method thereof 有权
标题翻译：具有包含含有金属，硅和氧的绝缘膜的栅极绝缘膜结构的半导体器件及其制造方法
公开(公告)号：US20080102616A1
公开(公告)日：2008-05-01
申请号：US11999958
申请日：2007-12-07
申请人： Yoshitaka Tsunashima , Seiji Ihumiya , Yasumasa Suizu , Yoshio Ozawa , Kiyotaka Miyano , Masayuki Tanaka
发明人： Yoshitaka Tsunashima , Seiji Ihumiya , Yasumasa Suizu , Yoshio Ozawa , Kiyotaka Miyano , Masayuki Tanaka
IPC分类号： H01L21/283
CPC分类号： H01L21/82345 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/31604 , H01L21/823462 , H01L21/823475 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6656
摘要： Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
摘要翻译：权利要求和公开的是一种半导体器件，包括具有在包含金属，硅和氧的金属硅酸盐的化合物中含有氮或氟的栅极绝缘膜结构的晶体管，具有非晶态金属氧化物层叠结构的栅极绝缘膜结构膜和金属硅酸盐膜，或具有包括第一金属元素的氧化物膜的第一栅极绝缘膜和包括第二金属元素的金属硅酸盐膜的第二栅极绝缘膜的栅极绝缘膜结构。

86. 发明申请

US20080012061A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20080012061A1
公开(公告)日：2008-01-17
申请号：US11687758
申请日：2007-03-19
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮置栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

87. 发明申请

US20070254434A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070254434A1
公开(公告)日：2007-11-01
申请号：US11819428
申请日：2007-06-27
申请人： Ichiro Mizushima , Yoshio Ozawa
发明人： Ichiro Mizushima , Yoshio Ozawa
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate including an active area (AA) surrounded by an isolation insulating film, and a nonvolatile memory cell on the AA, the nonvolatile memory cell including a tunnel insulating film on the AA, a FG electrode on the tunnel insulating film, a CG electrode above the FG electrode, and an interelectrode insulating film between the FG electrode and the CG electrode, relating to a cross section in a channel width direction of the nonvolatile memory cell, dimension in the channel width direction of a top surface of the AA is shorter than dimension in the channel width direction of a bottom surface of the tunnel insulating film, and an area of a portion opposing the AA of the tunnel insulating film is smaller than an area of a portion opposing a top surface of the FG electrode of the interelectrode insulating film.
摘要翻译：一种半导体器件包括：半导体衬底，包括由隔离绝缘膜包围的有源区（AA）和在AA上的非易失性存储单元，非易失性存储单元包括AA上的隧道绝缘膜，隧道绝缘上的FG电极薄膜，FG电极上方的CG电极以及FG电极和CG电极之间的电极间绝缘膜，涉及非易失性存储单元的沟道宽度方向上的横截面，顶表面的沟道宽度方向上的尺寸的距离短于隧道绝缘膜的底面的沟道宽度方向上的尺寸，并且与隧道绝缘膜的AA相对的部分的面积小于与隧道绝缘膜的顶面相对的部分的面积电极间绝缘膜的FG电极。

88. 发明申请

US20070218605A1 Semiconductor device and method of manufacture thereof 失效
公开(公告)号：US20070218605A1
公开(公告)日：2007-09-20
申请号：US11790033
申请日：2007-04-23
申请人： Yoshio Ozawa , Yasumasa Suizu , Yoshitaka Tsunashima
发明人： Yoshio Ozawa , Yasumasa Suizu , Yoshitaka Tsunashima
IPC分类号： H01L21/765
CPC分类号： H01L29/7881 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02233 , H01L21/02271 , H01L21/28044 , H01L21/28202 , H01L21/28247 , H01L21/28273 , H01L21/3144 , H01L27/115 , H01L27/11521 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66825 , H01L29/7833 , Y10S438/911 , Y10S438/942 , Y10S438/947 , Y10S438/966
摘要： A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.

89. 发明申请

US20070200168A1 MONOS type nonvolatile memory cell, nonvolatile memory, and manufacturing method thereof 审中-公开
标题翻译： MONOS型非易失性存储单元，非易失性存储器及其制造方法
公开(公告)号：US20070200168A1
公开(公告)日：2007-08-30
申请号：US11706999
申请日：2007-02-16
申请人： Yoshio Ozawa , Yoshitaka Tsunashima
发明人： Yoshio Ozawa , Yoshitaka Tsunashima
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/4234
摘要： A MONOS type nonvolatile memory cell is structured such that a laminated insulating film which is formed by sequentially laminating a tunnel insulating layer, a charge storage insulating layer, and a charge block insulating layer is provided on a convex curved surface portion of a semiconductor substrate, and a control gate electrode is further formed thereon. A thickness of the tunnel insulating layer is set to be 4 to 10 nm, and data writing/data erasing operations are carried out by making an F-N tunneling current flow in the tunnel insulating layer.
摘要翻译：构造为在半导体衬底的凸曲面部分上设置通过依次层叠隧道绝缘层，电荷存储绝缘层和电荷块绝缘层而形成的叠层绝缘膜的MONOS型非易失性存储单元，并且还在其上形成控制栅电极。将隧道绝缘层的厚度设定为4〜10nm，通过在隧道绝缘层中形成F-N隧道电流来进行数据写入/数据擦除动作。

90. 发明授权

US07183615B2 Nonvolatile semiconductor memory and manufacturing method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US07183615B2
公开(公告)日：2007-02-27
申请号：US10868773
申请日：2004-06-17
申请人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
发明人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L27/115 , H01L29/42324 , Y10T428/24256
摘要： A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.
摘要翻译：半导体存储器具有存储单元阵列，其包括（a）沿着列方向延伸的器件隔离膜，交替地布置在沿着行方向排列的存储单元晶体管之间，（b）沿行和列方向排列的第一导电层第一导电层的顶表面位于比器件隔离膜的顶表面更低的水平面上，（c）布置在器件隔离膜和第一导电层上的电极间电介质，使得电极间电介质可以由属于不同单元列的存储单元晶体管所共用，电极间电介质的相对介电常数高于器件隔离膜的相对介电常数，（d）沿着行方向延伸的第二导电层，在电极间电介质上。这里，器件隔离膜的上角被倒角。

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