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    • 81. 发明授权
    • Programmable logic device with power supply noise monitoring
    • 可编程逻辑器件,具有电源噪声监测功能
    • US07359811B1
    • 2008-04-15
    • US11153984
    • 2005-06-16
    • Hui Liu
    • Hui Liu
    • G05F1/40
    • G06F17/5054
    • Programmable logic device power supply noise levels are characterized using internal measurements. By making power supply noise measurements internally, noise measurements are made without influence from device packaging or circuit board environmental effects. The input-output circuitry of a programmable logic device is configured to supply a power supply voltage from the output of an output buffer to one of the inputs of a differential input buffer. The other of the inputs of the differential input buffer is provided with a reference voltage from an external voltage reference circuit. The differential input buffer serves as a comparator and generates an output signal based on a comparison of the power supply voltage from the output buffer and the reference voltage. A noise monitoring circuit processes the output of the input buffer. The noise monitoring circuit may be based on a register.
    • 可编程逻辑器件电源噪声电平采用内部测量表征。 通过内部进行电源噪声测量,噪声测量不受设备封装或电路板环境影响的影响。 可编程逻辑器件的输入输出电路被配置为将电源电压从输出缓冲器的输出提供给差分输入缓冲器的输入之一。 差分输入缓冲器的另一个输入端提供有来自外部参考电路的参考电压。 差分输入缓冲器用作比较器,并且基于来自输出缓冲器的电源电压与参考电压的比较来产生输出信号。 噪声监测电路处理输入缓冲器的输出。 噪声监测电路可以基于寄存器。
    • 82. 发明授权
    • Method and system for improving memory interface data integrity
    • 提高内存接口数据完整性的方法和系统
    • US07352299B1
    • 2008-04-01
    • US11560673
    • 2006-11-16
    • Hui Liu
    • Hui Liu
    • H03M7/00
    • G06F11/1032
    • An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder sets a status bit to indicate that the data are encoded. The encoder includes two encoding stages to further enhance the data integrity and transfer. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, including the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data. The decoder is connected in series with the parity checker.
    • 提供了一种用于优化到外部存储器接口总线的数据呈现的集成电路(IC)。 IC通过外部存储器接口总线与外部存储器通信。 该IC包括编码器,其可以对正在发送到外部存储器的数据进行编码。 编码器根据数据中大多数位的逻辑值对数据进行编码。 编码器设置状态位以指示数据被编码。 编码器包括两个编码级,以进一步增强数据的完整性和传输。 进一步与编码器串联的是奇偶校验发生器,其基于包括状态位在内的数据中的逻辑1的数量是偶数还是奇数来设置奇偶校验位逻辑值。 IC还包括一个奇偶校验器,用于检测在传输过程中数据是否发生错误。 IC内的解码器将数据解码为原始数据。 解码器与奇偶校验器串联连接。
    • 86. 发明申请
    • SYSTEM FOR IMPROVING MEMORY INTERFACE DATA INTEGRITY IN PLDS
    • 改进PLDS中记忆界面数据完整性的系统
    • US20060290542A1
    • 2006-12-28
    • US11458962
    • 2006-07-20
    • Hui Liu
    • Hui Liu
    • H03M7/34
    • G06F11/1032
    • An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder is capable of setting a status bit to indicate that the data are encoded. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, along with the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data.
    • 提供了一种用于优化到外部存储器接口总线的数据呈现的集成电路(IC)。 IC通过外部存储器接口总线与外部存储器通信。 该IC包括编码器,其可以对正在发送到外部存储器的数据进行编码。 编码器根据数据中大多数位的逻辑值对数据进行编码。 编码器能够设置状态位以指示数据被编码。 进一步与编码器串联的是奇偶校验发生器,其基于数据中的逻辑1的数量以及状态位是偶数还是奇数来设置奇偶校验位逻辑值。 IC还包括一个奇偶校验器,用于检测在传输过程中数据是否发生错误。 IC内的解码器将数据解码为原始数据。
    • 89. 发明授权
    • Smart antenna CDMA wireless communication system
    • 智能天线CDMA无线通信系统
    • US6122260A
    • 2000-09-19
    • US768100
    • 1996-12-16
    • Hui LiuGuanghan Xu
    • Hui LiuGuanghan Xu
    • H04B7/10H04B7/005H04B7/04H04B7/06H04B7/08H04B7/26H04J13/00
    • H04W52/42H04B7/0617H04B7/0632H04B7/086H04B7/0408Y02B60/50
    • A TDD antenna array S-CDMA system for increasing the capacity and quality of a wireless communications is disclosed. By simultaneous exploiting the spatial and code diversities, high performance communications between a plurality of remote terminals and a base station is achieved without sacrificing system flexibility and robustness. The time-division-duplex mode together with the inherent interference immunity of S-CDMA signals allow the spatial diversity to be exploited using simple and robust beamforming rather than demanding nulling. Measurements from an array of receiving antennas at the base station are utilized to estimate spatial signatures, timing offsets, transmission powers and other propagation parameters associated with a plurality of S-CDMA terminals. Such information is then used for system synchronization, downlink beamforming, as well as handoff management. In an examplary embodiment, the aforementioned processing is accomplished with minimum computations, thereby allowing the disclosed system to be applicable to a rapidly varying environment. Among many other inherent benefits of the present invention are large capacity and power efficiency, strong interference/fading resistance, robustness power control, and easy hand-off.
    • 公开了一种用于增加无线通信的容量和质量的TDD天线阵列S-CDMA系统。 通过同时利用空间和代码多样性,实现了多个远程终端与基站之间的高性能通信,而不牺牲系统灵活性和鲁棒性。 时分双工模式以及S-CDMA信号的固有抗干扰能力允许使用简单且鲁棒的波束成形来利用空间分集,而不是要求零点。 来自基站的接收天线阵列的测量被用于估计与多个S-CDMA终端相关联的空间签名,定时偏移,发射功率和其它传播参数。 然后将这样的信息用于系统同步,下行链路波束成形以及切换管理。 在示例性实施例中,通过最小计算来实现上述处理,从而允许所公开的系统适用于快速变化的环境。 本发明的许多其它固有的优点是具有大容量和功率效率,强的抗干扰/抗褪色性,鲁棒性功率控制和便于切换。