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81. 发明授权

US06505260B2 Computer system with adaptive memory arbitration scheme 失效
标题翻译：具有自适应内存仲裁方案的计算机系统
公开(公告)号：US06505260B2
公开(公告)日：2003-01-07
申请号：US09784690
申请日：2001-02-15
申请人： Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
发明人： Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
IPC分类号： G06F1318
CPC分类号： G06F13/1605
摘要： A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.
摘要翻译：计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。这样的方案可防止低优先级的设备变得“记忆不足”。因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务最迫切的要求。此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。

82. 发明授权

US06294772B1 Microwave probe applicator for physical and chemical processes 有权
公开(公告)号：US06294772B1
公开(公告)日：2001-09-25
申请号：US09584305
申请日：2000-05-31
申请人： Gary Roger Greene , Lois B. Jassie , Edward Earl King , Michael J. Collins
发明人： Gary Roger Greene , Lois B. Jassie , Edward Earl King , Michael J. Collins
IPC分类号： H05B680
CPC分类号： H05B6/806 , H05B6/70 , H05B6/72
摘要： A microwave heating system is disclosed for enhancing physical and chemical processes. The system includes a microwave source, an antenna having a cable, a receiver for receiving microwaves generated by the source, with the receiver being connected to a first end of the cable, and a transmitter for transmitting microwaves generated by the source, and with the transmitter being connected to an opposite end of the cable. The system also includes a reaction vessel with the transmitter inside the reaction vessel; and a microwave shield surrounding the transmitter for preventing microwaves emitted from the transmitter from extending substantially beyond the reaction vessel.

83. 发明授权

US06275885B1 System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache 有权
标题翻译：当将处理器总线的编程数量发送到处理器高速缓存时，维持处理器总线的所有权的系统和方法
公开(公告)号：US06275885B1
公开(公告)日：2001-08-14
申请号：US09164191
申请日：1998-09-30
申请人： Kenneth T. Chin , Michael J. Collins , John E. Larson , Robert A. Lester
发明人： Kenneth T. Chin , Michael J. Collins , John E. Larson , Robert A. Lester
IPC分类号： G06F1300
CPC分类号： G06F12/0831 , G06F13/16
摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid data exists within the CPU cache storage locations. If so, a writeback operation can occur. Ownership of the CPU bus is maintained by the bus interface unit during the snooping operation, as well as during writeback and the request of the memory bus by the peripheral-derived write cycle. It is not until ownership of the memory bus is granted by the memory arbiter that mastership is terminated by the bus interface unit. Accordingly, the bus interface unit keeps CPU-derived cycles off the CPU bus to ensure memory arbiter grants ownership to a write cycle from the peripheral bus. In this fashion, data from the peripheral bus can be stored in system memory before accessing that data by a CPU read cycle. The number of snoop cycles which the bus interface unit can initiate is determined by configuration registers programmed during power on, reset or boot up of computer.
摘要翻译：提供一种计算机，其具有耦合在CPU总线，外围总线（即PCI总线和/或图形总线）之间的总线接口单元和存储器总线。总线接口单元包括链接到相应总线的控制器，以及放置在各种控制器之间的地址和数据路径内的多个队列。外设总线控制器可以将写周期解码为存储器，然后处理器控制器可以请求并授予CPU本地总线的所有权。然后可以窥探写周期的地址，以确定CPU高速缓存存储位置中是否存在有效数据。如果是这样，可以进行回写操作。 CPU总线的所有权在侦听操作期间由总线接口单元维护，以及通过外设来源的写周期在写回和存储器总线的请求期间保持。直到存储器总线的所有权由总线接口单元终止主存的存储器仲裁器才被授予。因此，总线接口单元将CPU派生的周期从CPU总线保持，以确保存储器仲裁器将所有权授予来自外设总线的写周期。以这种方式，通过CPU读取周期访问该数据之前，来自外围总线的数据可以存储在系统存储器中。总线接口单元可以启动的窥探周期数由计算机上电，复位或启动时编程的配置寄存器决定。

84. 发明授权

US06227041B1 Method and apparatus for measuring volatile content 有权
标题翻译：用于测量挥发物含量的方法和装置
公开(公告)号：US06227041B1
公开(公告)日：2001-05-08
申请号：US09156086
申请日：1998-09-17
申请人： Michael J. Collins , William Edward Jennings
发明人： Michael J. Collins , William Edward Jennings
IPC分类号： G01N502
CPC分类号： G01N22/04 , G01N1/44 , G01N5/045
摘要： A method and associated apparatus are disclosed for measuring volatile content of samples that are particularly suitable for samples that tend to bum when heated. The method includes the steps of applying microwave radiation at a predetermined power level to a moisture-containing sample to drive volatiles from the sample, monitoring the weight of the sample during the application of microwave power, monitoring the temperature of the sample during the application of microwave power without contacting either the sample or anything in contact with the sample, and moderating the microwave power being applied to the sample based upon the monitored temperature to maintain the temperature of the sample at or below a pre-determined set point temperature below which the sample will not bum. In its apparatus aspects, the invention includes a cavity for holding a sample for which the volatile content is to be determined; an infrared photosensor positioned to measure the temperature of a sample placed within the cavity, an analytical balance for measuring the weight of the sample while the sample is in the cavity, a power source for introducing microwaves into the cavity, and a processing unit in communication with the infrared photosensor and the power source for controlling the introduction of microwave energy to the cavity in response to the infrared photosensor to prevent the sample from reaching temperatures at which the sample would burn.
摘要翻译：公开了一种用于测量样品的挥发性含量的方法和相关装置，其特别适用于在加热时易于燃烧的样品。该方法包括以下步骤：将预定功率水平的微波辐射施加到含水样品以驱动来自样品的挥发物，在施加微波功率期间监测样品的重量，在施用微波功率期间监测样品的温度微波功率，而不接触样品或任何与样品接触的物质，并根据监测的温度调节施加到样品的微波功率，以将样品的温度维持在或低于预定的设定点温度，样品不会烧伤。在其装置方面，本发明包括用于保持要确定挥发物含量的样品的空腔; 定位成测量放置在空腔内的样品的温度的红外光电传感器，用于在样品处于空腔中时测量样品的重量的分析天平，用于将微波引入空腔的电源以及通信处理单元红外光电传感器和电源用于响应于红外光电传感器控制将微波能量引入空腔，以防止样品达到样品燃烧的温度。

85. 发明授权

US6115791A Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control 失效
标题翻译：基于监视和解码处理器总线周期进行冲洗/清除序列控制的分层缓存系统冲洗方案
公开(公告)号：US6115791A
公开(公告)日：2000-09-05
申请号：US48577
申请日：1998-03-26
申请人： Michael J. Collins , Gary W. Thome
发明人： Michael J. Collins , Gary W. Thome
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0897
摘要： An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.
摘要翻译：一种用于在解码特殊冲洗确认周期时监视和解码处理器总线周期并刷新第二级高速缓存的装置。 CPU优选地包括内部高速缓存和用于接收命令CPU冲洗其内部高速缓存的信号的刷新输入。通过执行任何必要的循环来刷新脏数据到主存储器后，CPU执行特殊的刷新确认周期，以通知外部设备冲洗过程已经完成。缓存控制器检测刷新确认周期，并向第二级缓存提供刷新信号。然后，缓存控制器向CPU提供周期信号的结束以指示冲洗周期已被确认。

86. 发明授权

US5949436A Accelerated graphics port multiple entry gart cache allocation system and method 失效
标题翻译：加速图形端口多进入gart缓存分配系统和方法
公开(公告)号：US5949436A
公开(公告)日：1999-09-07
申请号：US941861
申请日：1997-09-30
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Jerome J. Johnson , Michael J. Collins
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Jerome J. Johnson , Michael J. Collins
IPC分类号： G06F12/10 , G06T1/60 , G06F15/00 , G06T1/00
CPC分类号： G06T1/60 , G06F12/1027 , G06F12/1081
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. When a GART table entry is not found in the cache, a memory access is required to obtained the needed GART table entry. There are two GART table entries in each quadword returned in toggle mode of the cacheline of memory information returned from the memory read access. At least one quadword (two GART table entries) are stored in the cache each time a memory access is required because of a cache miss.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）由核心逻辑芯片组使用，将AGP图形控制器使用的虚拟内存地址重新映射到驻留在计算机系统内存中的物理内存地址GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际使用不连续的块或物理系统存储器的页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针。核心逻辑芯片组可以缓存最近使用的GART表项的子集，以在执行地址转换时提高AGP性能。当缓存中没有找到GART表条目时，需要内存访问才能获取所需的GART表条目。在内存读取访问返回的内存信息的缓存行的切换模式下，每个四字中有两个GART表条目。由于缓存未命中，每次需要存储器访问时，至少有一个四字（两个GART表条目）存储在缓存中。

87. 发明授权

US5796992A Circuit for switching between synchronous and asynchronous memory refresh cycles in low power mode 失效
标题翻译：用于在低功耗模式下在同步和异步存储器刷新周期之间切换的电路
公开(公告)号：US5796992A
公开(公告)日：1998-08-18
申请号：US575370
申请日：1995-12-20
申请人： James R. Reif , Michael J. Collins , Todd J. DeSchepper
发明人： James R. Reif , Michael J. Collins , Todd J. DeSchepper
IPC分类号： G06F1/32 , G06F1/04
CPC分类号： G06F1/32
摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.
摘要翻译：一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和待机模式。计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。如果为真，则CPU-PCI桥转换到空闲模式。电源管理电路在空闲或待机模式下也执行低功耗刷新周期。在这些模式下，CPU-PCI桥接器中的存储器控制器被禁用以节省电力。电源管理电路基于外部异步时钟执行刷新周期。此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于存在连接到PCI总线的3.3伏和5伏组件的混合而引起的漏电流。

88. 发明授权

US5721935A Apparatus and method for entering low power mode in a computer system 失效
标题翻译：在计算机系统中进入低功率模式的装置和方法
公开(公告)号：US5721935A
公开(公告)日：1998-02-24
申请号：US801200
申请日：1997-02-18
申请人： Todd J. DeSchepper , James R. Reif , James R. Edwards , Michael J. Collins , John E. Larson
发明人： Todd J. DeSchepper , James R. Reif , James R. Edwards , Michael J. Collins , John E. Larson
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282
摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.
摘要翻译：一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和待机模式。计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。如果为真，则CPU-PCI桥转换到空闲模式。电源管理电路在空闲或待机模式下也执行低功耗刷新周期。在这些模式下，CPU-PCI桥接器中的存储器控制器被禁用以节省电力。电源管理电路基于外部异步时钟执行刷新周期。此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于存在连接到PCI总线的3.3伏和5伏组件的混合而引起的漏电流。

89. 发明授权

US5537555A Fully pipelined and highly concurrent memory controller 失效
标题翻译：完全流水线和高度并发的内存控制器
公开(公告)号：US5537555A
公开(公告)日：1996-07-16
申请号：US34290
申请日：1993-03-22
申请人： John A. Landry , Gary W. Thome , Paul A. Santeler , Randy M. Bonella , Michael J. Collins
发明人： John A. Landry , Gary W. Thome , Paul A. Santeler , Randy M. Bonella , Michael J. Collins
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16 , G06F13/00
CPC分类号： G06F13/1615
摘要： A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine completes its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.
摘要翻译：一个内存控制器，最大程度地利用任何处理器流水线并同时运行大量的周期。存储器控制器可以利用不同的速度存储器件并以其期望的最佳速度运行每个存储器件。这些功能由多个简单的相互依赖的状态机执行，每个状态机负责整个操作的一小部分。当每个状态机完成其功能时，它通知相关的状态机它现在可以继续，并继续等待下一个启动或继续指示。下一台状态机以类似的方式运行。负责循环早期部分的状态机在下一个循环中开始执行任务，然后负责循环后期部分的状态机完成任务。存储器控制器在逻辑上组织为三个主要块，前端块，存储器块和主机块，每个都负责与其相关总线和组件的交互，并与各种其他块进行交互。存储器控制器使用不同的速度存储器件，例如60ns和80ns，各个存储器件以其完全设计的速率工作。存储器的速度存储每个128 KB的存储器块，并且当发生存储器周期以重定向状态机时使用，实现存储器件的定时改变。

90. 发明授权

US5348713A Recovery of metal values from zinc plant residues 失效
标题翻译：从锌植物残渣回收金属价值
公开(公告)号：US5348713A
公开(公告)日：1994-09-20
申请号：US929927
申请日：1992-08-14
申请人： Derek E. Kerfoot , Michael J. Collins , Michael E. Chalkley
发明人： Derek E. Kerfoot , Michael J. Collins , Michael E. Chalkley
IPC分类号： C22B7/00 , C22B15/00 , C22B19/30 , C22B3/08
CPC分类号： C22B13/045 , C22B11/042 , C22B15/0067 , C22B19/22 , C22B19/30 , C22B7/007 , Y02P10/214 , Y02P10/234 , Y02P10/236
摘要： A process is disclosed for recovering zinc, lead, copper and precious metals from zinc plant residue, said process comprising leaching the residue with return zinc spent electrolyte, neutralizing residual acid and reducing ferric iron in the solution by addition of zinc sulphide concentrate in the presence of a limited quantity of oxygen, flotation of the resulting slurry to separate unreacted zinc sulphide, treatment of flotation tailings with sulphur dioxide and elemental sulphur to further leach iron, zinc and impurity elements and precipitate copper, flotation of the resulting slurry to separate a copper sulphide concentrate, thickening, filtering and washing of the flotation tailings followed by addition of lime and sodium sulphide to activate lead sulphate and flotation of a lead concentrate from the residue. Iron and impurity elements are precipitated from the copper flotation tailings thickener overflow solution by addition of zinc hydroxide sludge, lime and oxygen to produce a high strength, iron free zinc sulphate solution.
摘要翻译：公开了一种用于从锌植物残渣中回收锌，铅，铜和贵金属的方法，所述方法包括用返回的锌废电解液浸出残余物，通过在存在下加入硫化锌浓缩物中和残留酸和还原三价铁，还原三价铁的有限量的氧气，所得浆料的浮选以分离未反应的硫化锌，用二氧化硫和元素硫处理浮选尾矿以进一步浸出铁，锌和杂质元素并沉淀铜，将所得浆液浮选分离铜硫化物浓缩物，增稠，过滤和洗涤浮选尾矿，然后加入石灰和硫化钠以活化硫酸铅并从残余物中浮选铅精矿。通过加入氢氧化锌污泥，石灰和氧气，从铜浮选尾矿增稠剂溢流溶液中沉淀出铁和杂质元素，产生高强度的无铁硫酸锌溶液。

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