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81. 发明授权

US06678204B2 Semiconductor memory device with high-speed operation and methods of using and designing thereof 有权
标题翻译：具有高速操作的半导体存储器件及其使用和设计方法
公开(公告)号：US06678204B2
公开(公告)日：2004-01-13
申请号：US10026755
申请日：2001-12-27
申请人： Osamu Nagashima , Joseph Dominic Macri
发明人： Osamu Nagashima , Joseph Dominic Macri
IPC分类号： G11C812
CPC分类号： G11C11/4076 , G11C7/1042 , G11C7/1072 , G11C7/22 , G11C11/4097
摘要： Two types of command interval specifications are defined as first and second command interval specifications. The first command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the second command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command is executed during the column circuits precharge after the preceding command. Therefore, in the case of the second command interval specification, a command interval is substantially shortened. In addition, pairs of banks are defined as bank pairs, and are applied the first and second command interval specifications, so that the DRAM device is small-sized.
摘要翻译：两种类型的命令间隔规范被定义为第一和第二命令间隔规范。第一个命令间隔规范被定义为为同一个组发出的上一个命令和后续命令之间的关系，而第二个命令间隔规范被定义为前面的命令和下一个命令之间的关系，银行。对于第二命令间隔指定，由于在前一命令和后续命令之间的目标组不同，所以在前一命令之后的列电路预充电期间执行以下命令。因此，在第二命令间隔指定的情况下，命令间隔大大缩短。另外，银行对被定义为银行对，并且应用第一和第二指令间隔规范，使得DRAM设备是小型的。

82. 发明授权

US06396761B2 Semiconductor integrated circuit device and method of activating the same 有权
标题翻译：半导体集成电路器件及其激活方法
公开(公告)号：US06396761B2
公开(公告)日：2002-05-28
申请号：US09875169
申请日：2001-06-07
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
摘要翻译：动态RAM被分成响应于从外部端子提供的输入信号的输入电路块，包括操作开始信号，响应于从输入电路块输入的信号而被激活的内部电路块，以及输出电路块用于将从内部电路块输出的信号输出到外部端子。在用于施加从外部端子提供的工作电压的电力线和用于内部电路块中的第一电路部分的内部电力线之间的并行形式提供多个开关MOSFET，其不需要在其非正常状态下的存储操作操作状态。此外，响应于通过延迟通过输入电路块提供的启动信号而产生的控制信号，开关MOSFET逐步导通，以便执行每个工作电压的供应。

83. 发明授权

US06385100B2 Semiconductor memory device with improved column selecting operation 有权
标题翻译：具有改进的列选择操作的半导体存储器件
公开(公告)号：US06385100B2
公开(公告)日：2002-05-07
申请号：US09789753
申请日：2001-02-22
申请人： Hiromasa Noda , Youji Idei , Osamu Nagashima , Tetsuo Ado
发明人： Hiromasa Noda , Youji Idei , Osamu Nagashima , Tetsuo Ado
IPC分类号： G11C700
CPC分类号： G11C29/84 , G11C7/1027 , G11C8/04 , G11C11/4087
摘要： A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.
摘要翻译：一种半导体存储器件具有列地址解码器，它包括分别对应于高阶和低阶地址的第一和第二预解码器，用于使用第二预解码器的输出信号作为初始值的移位寄存器，以及输出电路，用于根据动作模式选择第二预解码器的输出信号或移位寄存器的输出信号。选择信号由第一预解码器的输出信号和通过输出电路的输出信号形成。移位寄存器包括用于偶数地址的第一移位寄存器和奇数地址的第二移位寄存器，并且基于顺序动作和交错动作形成位线的两组连续选择信号通过组合其上下移动动作的初始值。

84. 发明授权

US5724297A Semiconductor integrated circuit device and method of activating the same 失效
公开(公告)号：US5724297A
公开(公告)日：1998-03-03
申请号：US762883
申请日：1996-12-12
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , H03K19/00 , H03K17/16
CPC分类号： G11C5/14 , G11C11/4074 , G11C5/147 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

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