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81. 发明授权

US11061682B2 Advanced processor architecture 有权
公开(公告)号：US11061682B2
公开(公告)日：2021-07-13
申请号：US15535697
申请日：2015-12-13
申请人： Martin Vorbach , Hyperion Core, Inc.
发明人： Martin Vorbach
IPC分类号： G06F9/38 , G06F9/30 , G06F9/32
摘要： The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).

82. 发明授权

US09703538B2 Tool-level and hardware-level code optimization and respective hardware modification 有权
公开(公告)号：US09703538B2
公开(公告)日：2017-07-11
申请号：US14124636
申请日：2012-06-06
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： G06F9/44 , G06F9/45 , G06F17/50
CPC分类号： G06F8/443 , G06F8/4434 , G06F8/447 , G06F17/504 , G06F17/5045 , G06F17/5054
摘要： The present invention relates to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.

83. 发明授权

US09348587B2 Providing code sections for matrix of arithmetic logic units in a processor 有权
标题翻译：为处理器中的算术逻辑单元的矩阵提供代码段
公开(公告)号：US09348587B2
公开(公告)日：2016-05-24
申请号：US13809159
申请日：2011-07-08
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： G06F9/30 , G06F9/32 , G06F9/355 , G06F9/38
CPC分类号： G06F9/381 , G06F9/3001 , G06F9/30043 , G06F9/30054 , G06F9/30058 , G06F9/30065 , G06F9/30072 , G06F9/30076 , G06F9/30094 , G06F9/30098 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/325 , G06F9/355 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3887 , G06F9/3889
摘要： The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyzer unit located between the trace cache and the ALUs, wherein the analyzer unit analyzes the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
摘要翻译：本发明涉及具有跟踪高速缓存和排列成矩阵的多个ALU的处理器，包括位于跟踪高速缓存和ALU之间的分析器单元，其中分析器单元分析跟踪高速缓存中的代码，检测循环，变换所述代码和所述代码的ALU部分的组合结合到用于多个时钟周期的联合执行的块。

84. 发明申请

US20140143509A1 METHOD AND DEVICE FOR DATA PROCESSING 审中-公开
标题翻译：用于数据处理的方法和装置
公开(公告)号：US20140143509A1
公开(公告)日：2014-05-22
申请号：US14162704
申请日：2014-01-23
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： G06F3/06
CPC分类号： G06F8/447
摘要： The present provides a method for operating a module by a processor. The method includes generating, by at least one task being executed on the processor, control information for controlling operation of the module. The module includes an arrangement of a plurality of cells, including a bus system. At least some of the cells having arithmetic and logic units. At least some of the cells being arranged in at least two dimensions. The method further including writing, by the processor, the control information into a memory being shared with the module in a list-like manner to form a list of operations. The method further including executing, by the module, the operations listed in the list.
摘要翻译：本发明提供了一种由处理器操作模块的方法。该方法包括通过在处理器上执行的至少一个任务生成用于控制模块的操作的控制信息。该模块包括多个单元的布置，包括总线系统。至少一些具有算术和逻辑单元的单元。至少一些单元被布置在至少两个维度中。该方法还包括由处理器将控制信息以类似列表的方式写入与模块共享的存储器中，以形成操作列表。该方法还包括由模块执行列表中列出的操作。

85. 发明授权

US08407525B2 Method for debugging reconfigurable architectures 有权
公开(公告)号：US08407525B2
公开(公告)日：2013-03-26
申请号：US13279561
申请日：2011-10-24
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： G06F11/00
CPC分类号： G06F11/26 , G06F9/30036 , G06F11/267 , G06F11/3656 , G06F15/7867
摘要： A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle into a memory, which is then analyzed by the debugger.

86. 发明授权

US08069373B2 Method for debugging reconfigurable architectures 有权
标题翻译：调试可重构架构的方法
公开(公告)号：US08069373B2
公开(公告)日：2011-11-29
申请号：US12354590
申请日：2009-01-15
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： G06F11/00
CPC分类号： G06F11/26 , G06F9/30036 , G06F11/267 , G06F11/3656 , G06F15/7867
摘要： A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle into a memory, which is then analyzed by the debugger.
摘要翻译：描述了一种用于调试可重配置硬件的方法。根据该方法，将所有必需的调试信息在每个配置周期中写入存储器，然后由调试器分析。

87. 发明授权

US07996827B2 Method for the translation of programs for reconfigurable architectures 有权
标题翻译：翻译可重构架构程序的方法
公开(公告)号：US07996827B2
公开(公告)日：2011-08-09
申请号：US10486771
申请日：2002-08-16
申请人： Martin Vorbach , May Frank , Armin Nückel
发明人： Martin Vorbach , May Frank , Armin Nückel
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/447
摘要： A method for advantageously translating high-level language codes for data processing using a reconfigurable architecture, memories addressable internally from within said reconfigurable architecture, and memories external to said reconfigurable architecture, may include constructing a finite automaton for computation in such a way that a complex combinatory network of individual functions is formed, assigning memories to the network for storage of operands and results, and separating external memory accesses for providing a transfer of at least one of operands and results as data from an external memory to a memory addressable internally by the reconfigurable architecture.
摘要翻译：一种用于有利地翻译用于使用可重新配置架构的数据处理的高级语言代码的方法，可从内部从所述可重新配置架构内寻址的存储器和所述可重新配置架构外部的存储器的方法可以包括构建用于计算的有限自动机，形成各个功能的组合网络，将存储器分配给存储操作数和结果的存储器，以及分离外部存储器存取，以提供作为数据的操作数和结果中的至少一个的操作数和结果的传输从外部存储器到内部可寻址的存储器可重构架构。

88. 发明申请

US20110161977A1 METHOD AND DEVICE FOR DATA PROCESSING 审中-公开
标题翻译：用于数据处理的方法和装置
公开(公告)号：US20110161977A1
公开(公告)日：2011-06-30
申请号：US12729932
申请日：2010-03-23
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： Designing a coupling of a traditional processor, in particular a sequential processor, and a reconfigurable field of data processing units, in particular a runtime-reconfigurable field of data processing units is described.
摘要翻译：描述了传统处理器，特别是顺序处理器以及数据处理单元的可重新配置字段（特别是数据处理单元的运行时可重新配置的字段）的耦合。

89. 发明授权

US07822881B2 Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like) 有权
标题翻译：数据流处理器（DFP）和具有二维或三维可编程单元结构（FPGA，DPGAs等）的单元的自动动态重新加载的过程
公开(公告)号：US07822881B2
公开(公告)日：2010-10-26
申请号：US11246617
申请日：2005-10-07
申请人： Martin Vorbach , Robert Münch
发明人： Martin Vorbach , Robert Münch
IPC分类号： G06F3/00 , G06F15/76
CPC分类号： G06F15/7867 , H03K19/17752 , H03K19/17756 , H03K19/1776 , H03K19/17776
摘要： In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.
摘要翻译：在数据处理方法中，可以使用多个可配置的粗粒度元素来获得第一结果数据，第一结果数据可以被写入到包括空间上分离的第一和第二存储器区域并且经由总线连接到可以随后从存储器中读出多个可配置的粗粒度元素，第一结果数据可以随后使用多个可配置的粗粒度元素进行处理。在第一配置中，第一存储器区域可以被配置为写入存储器，并且第二存储器区域可以被配置为读取存储器。在根据第一配置写入和读取存储器之后，第一存储器区域可以被配置为读取存储器，并且第二存储器区域可以被配置为写入存储器。

90. 发明授权

US07782087B2 Reconfigurable sequencer structure 有权
标题翻译：可重新配置的音序器结构
公开(公告)号：US07782087B2
公开(公告)日：2010-08-24
申请号：US12541299
申请日：2009-08-14
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： H03K19/173
CPC分类号： G06F15/7867 , G06F9/30145 , G06F13/16 , G06F13/36 , G06F13/4068 , H03K19/173
摘要： A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.
摘要翻译：描述用于数据处理的单元元素字段，具有用于执行代数和/或逻辑功能的功能单元装置和用于接收，存储和/或输出信息的存储单元装置。形成功能单元 - 存储单元组合，其中控制连接从功能单元装置引导到存储单元装置。

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