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81. 发明授权

US06201278B1 Trench transistor with insulative spacers 失效
标题翻译：带绝缘垫片的沟槽晶体管
公开(公告)号：US06201278B1
公开(公告)日：2001-03-13
申请号：US09028896
申请日：1998-02-24
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L31062
CPC分类号： H01L29/7834 , H01L29/66621
摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.
摘要翻译：公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与栅电极。有利地，沟道长度明显小于沟槽长度。

82. 发明授权

US6100146A Method of forming trench transistor with insulative spacers 失效
标题翻译：用绝缘间隔物形成沟槽晶体管的方法
公开(公告)号：US6100146A
公开(公告)日：2000-08-08
申请号：US739595
申请日：1996-10-30
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7834 , H01L29/66621
摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.
摘要翻译：公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与栅电极。有利地，沟道长度明显小于沟槽长度。

83. 发明授权

US6093611A Oxide liner for high reliability with reduced encroachment of the source/drain region 失效
标题翻译：氧化物衬垫具有高可靠性，减少了源极/漏极区域的侵入
公开(公告)号：US6093611A
公开(公告)日：2000-07-25
申请号：US994502
申请日：1997-12-19
申请人： Mark I. Gardner , Derick Wristers , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Derick Wristers , H. Jim Fulford, Jr.
IPC分类号： H01L21/762 , H01L21/336 , H01L21/76
CPC分类号： H01L21/76224
摘要： A semiconductor process in which a first nitrogen bearing oxide is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then formed on the nitrogen bearing oxide. The first oxide and the silicon nitride layer are then patterned to expose an upper surface of the substrate over a trench region of the substrate. An isolation trench is then etched into the trench region of the substrate and a nitrogen bearing liner oxide is then formed on sidewalls and a floor of the trench. An isolation dielectric is then formed within the trench and, thereafter, the silicon nitride layer is removed from the wafer. A suitable thickness of the first nitrogen bearing oxide and of the liner oxide is in the range of approximately 30 to 100 angstroms. A consumption of adjacent active regions caused by the thermal oxidation process is preferably less than approximately 50 angstroms.
摘要翻译：在半导体衬底的上表面上形成第一含氮氧化物的半导体工艺。然后在含氮氧化物上形成氮化硅层。然后将第一氧化物和氮化硅层图案化以在衬底的沟槽区域上露出衬底的上表面。然后将隔离沟槽蚀刻到衬底的沟槽区域中，然后在沟槽的侧壁和底板上形成含氮衬里氧化物。然后在沟槽内形成隔离电介质，然后从晶片上去除氮化硅层。第一含氮氧化物和衬里氧化物的合适厚度在约30至100埃的范围内。由热氧化过程引起的相邻活性区域的消耗优选小于约50埃。

84. 发明授权

US06080629A Ion implantation into a gate electrode layer using an implant profile displacement layer 失效
标题翻译：使用植入物轮廓位移层将离子注入到栅极电极层中
公开(公告)号：US06080629A
公开(公告)日：2000-06-27
申请号：US837579
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/28035
摘要： A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into underlying structures.
摘要翻译：将掺杂剂注入到薄栅电极层中的方法包括在栅电极层上形成位移层以形成组合位移/栅极电极层，并将掺杂剂注入到组合层中。注入的掺杂剂分布基本上完全位于栅极电极层内，或者基本上部分地位于栅极电极层内部分地位于位移层内。如果位移层最终被去除，则注入的掺杂剂的至少一部分保留在栅电极层内。栅极电极层可以在图案化之前或之后被注入，并蚀刻栅电极层以限定栅电极。此外，可以使用两种不同的选择性植入来限定不同掺杂剂浓度的分开的区域，例如P型多晶硅和N型多晶硅区域。每个区域可以利用单独的位移层厚度，这允许不同原子质量的掺杂剂使用类似的注入能量。可以使用较高的注入能量来掺杂比正常范围统计要求更薄的栅极电极层，而不会使植入物渗入下面的结构。

85. 发明授权

US6072192A Test structure responsive to electrical signals for determining lithographic misalignment of vias relative to electrically active elements 失效
标题翻译：响应于电信号的测试结构，用于确定通孔相对于电活性元件的光刻不对准
公开(公告)号：US6072192A
公开(公告)日：2000-06-06
申请号：US252365
申请日：1999-02-18
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
IPC分类号： G01R31/28 , G03F7/20 , H01L23/58 , H01L23/544
CPC分类号： G03F7/70633 , G01R31/2805 , G03F7/70658 , G01R31/2813
摘要： The present invention advantageously provides a method for determining lithographic misalignment of a via relative to an electrically active area. An electrically measured test structure is provided which is designed to have targeted via areas shifted from the midline(s) of a targeted active area(s). Further, the test structure is designed to have a test pad(s) that electrically communicates with the targeted active area(s). Design specifications of the test structure require the targeted via areas to be offset from the midline(s) of the active area(s) by varying distances. The above-mentioned method involves processing the designed test structure. An electrical signal may then be applied to conductors coupled to each of the vias while it is also being applied to the test pad. The resulting electrical response should be proportional to the distance that a via is misaligned from its desired location. Using the electrical responses for all the vias, it is possible to determine the direction and amount of misalignment.
摘要翻译：本发明有利地提供了一种用于确定通孔相对于电活动区域的光刻未对准的方法。提供电测量的测试结构，其被设计成具有从目标有源区域的中线偏移的目标通孔区域。此外，测试结构被设计成具有与目标有源区域电连通的测试焊盘。测试结构的设计规范要求目标通孔区域通过变化的距离偏离有效区域的中线。上述方法涉及处理设计的测试结构。然后可以将电信号施加到耦合到每个通孔的导体，同时它也被施加到测试垫。所产生的电响应应与通孔与其所需位置不对准的距离成正比。使用所有通孔的电响应，可以确定未对准的方向和量。

86. 发明授权

US6048785A Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching 失效
标题翻译：半导体制造方法，其使用片段拼接来组合由标线片图像定义的多个场
公开(公告)号：US6048785A
公开(公告)日：2000-04-11
申请号：US876628
申请日：1997-06-16
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76895 , Y10S438/946 , Y10S438/949
摘要： Each region of multiple regions on a semiconductor substrate is imaged in an exposure field defined by a reticle. The regions are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The regions are interconnected by imaging using a stitching reticle having an exposure field overlapping a plurality of the regions. The combination of reticle-imaged fields effectively increases the size of a field formed using a step and repeat technique while achieving high imaging resolution within the combined regions. Similarly, a plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are interconnected using a stitch mask and etch operation that combines the regions.
摘要翻译：在半导体衬底上的多个区域的每个区域以由掩模版定义的曝光区域成像。这些区域通过诸如场氧化物或沟槽隔离的隔离在半导体衬底内分离和电隔离。这些区域通过使用具有与多个区域重叠的曝光场的拼接掩模版进行成像来互连。掩模版成像场的组合有效地增加了使用步骤和重复技术形成的场的大小，同时在组合区域内实现高成像分辨率。类似地，使用多个集成芯片组中的每一个的单独掩模版成像，在单个半导体晶片上构造包括微处理器，存储器和支持芯片的多个集成芯片组。使用组合这些区域的针迹掩模和蚀刻操作来使不同的电路互连。

87. 发明授权

US6008109A Trench isolation structure having a low K dielectric encapsulated by oxide 失效
标题翻译：具有由氧化物包封的低K电介质的沟槽隔离结构
公开(公告)号：US6008109A
公开(公告)日：1999-12-28
申请号：US995121
申请日：1997-12-19
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Charles E. May
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Charles E. May
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76237
摘要： A process is provided for forming a trench isolation structure which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas separated by the trench isolation structure, being directly proportional to K, is thus reduced. As a result, the lateral width of the isolation structure may be decreased without significantly increasing the capacitance between those active areas. In an embodiment, a trench is etched within a semiconductor substrate upon which a masking layer is formed. An oxide liner is thermally grown upon the sidewalls and base of the trench. A low K dielectric material is formed within the trench such that its upper surface is level with the upper surface of the substrate. A fill oxide is then formed across the upper surface of the dielectric material. The resulting trench isolation structure includes a low K dielectric material encapsulated by some form of oxide. The trench isolation structure is less likely to experience current leakage during the operation of an ensuing integrated circuit employing the isolation structure.
摘要翻译：提供了一种用于形成沟槽隔离结构的工艺，该沟槽隔离结构包括具有相对较低的介电常数K的绝缘材料，K大约小于3.8。由沟槽隔离结构隔开的与K成正比的有源区之间的电容因此减小。结果，可以减小隔离结构的横向宽度，而不显着增加这些有源区域之间的电容。在一个实施例中，在形成有掩模层的半导体衬底内蚀刻沟槽。在沟槽的侧壁和基底上热生长氧化物衬垫。在沟槽内形成低K电介质材料，使得其上表面与衬底的上表面平齐。然后在电介质材料的上表面上形成填充氧化物。所形成的沟槽隔离结构包括由某种形式的氧化物封装的低K电介质材料。在采用隔离结构的随后的集成电路的操作期间，沟槽隔离结构不太可能经历电流泄漏。

88. 发明授权

US5970347A High performance mosfet transistor fabrication technique 失效
标题翻译：高性能mosfet晶体管制造技术
公开(公告)号：US5970347A
公开(公告)日：1999-10-19
申请号：US896400
申请日：1997-07-18
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28211 , H01L21/28176 , H01L29/4916 , H01L29/518 , H01L29/66659 , H01L29/7835
摘要： A semiconductor fabrication process in which nitrogen is incorporated into the transistor gate without significantly increasing the resistivity of the source/drain region. The incorporation of nitrogen into the gate structure substantially reduces the migration of impurity dopants from the silicon gate into the transistor channel region resulting in a more stable and reliable transistor. In one embodiment, a tail of the nitrogen impurity distribution incorporated into the gate structure extends into the channel region of the semiconductor substrate. In this embodiment, the nitrogen within the channel region prevents excessive lateral diffusion of source/drain impurities thereby permitting the fabrication of deep sub-micron transistors.
摘要翻译：其中氮被并入晶体管栅极而不显着增加源极/漏极区的电阻率的半导体制造工艺。将氮结合到栅极结构中大大减少了杂质掺杂剂从硅栅极迁移到晶体管沟道区域中，导致更稳定和可靠的晶体管。在一个实施例中，结合到栅极结构中的氮杂质分布的尾部延伸到半导体衬底的沟道区域中。在该实施例中，通道区域内的氮防止源/漏杂质的过度横向扩散，从而允许制造深亚微米晶体管。

89. 发明授权

US5937299A Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls 失效
标题翻译：用于形成具有硅化物源极/漏极接触的IGFET的方法，其紧邻具有倾斜侧壁的栅极
公开(公告)号：US5937299A
公开(公告)日：1999-08-10
申请号：US837522
申请日：1997-04-21
申请人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
发明人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/08 , H01L29/417 , H01L29/423
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/0847 , H01L29/41775 , H01L29/42376 , H01L29/66628 , H01L29/665
摘要： An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide. In this manner, a highly miniaturized IGFET can be provided with densely-packed gate, source and drain contacts without the need for sidewall spacers adjacent to the gate.
摘要翻译：公开了具有源极和漏极触点的IGFET，其紧邻具有倾斜侧壁的栅极。制造IGFET的方法包括在半导体衬底上形成栅极，其中栅极包括顶表面，底表面和相对的侧壁，并且顶表面具有比底表面大得多的长度，形成源极和漏极延伸到衬底中，在栅极，源极和漏极上沉积接触材料，以及在栅极上形成栅极接触，源极上的源极接触和漏极上的漏极接触。由于栅极侧壁的逆向斜坡，栅极与源极和漏极接触分离，并且由于接触材料中缺少台阶覆盖，栅极接触与源极和漏极接触分离。优选地，接触材料是难熔金属，并且通过将难熔金属转化为硅化物形成触点。以这种方式，高度小型化的IGFET可以设置有密集封装的栅极，源极和漏极接触，而不需要邻近栅极的侧壁间隔。

90. 发明授权

US5923980A Trench transistor with localized source/drain regions implanted through voids in trench 失效
标题翻译：具有通过沟槽中的空隙注入局部源/漏区的沟槽晶体管
公开(公告)号：US5923980A
公开(公告)日：1999-07-13
申请号：US739592
申请日：1996-10-30
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Frederick N. Hause
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Frederick N. Hause
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78 , H01L21/00 , H01L21/265
CPC分类号： H01L29/66621 , H01L21/28114 , H01L29/42376 , H01L29/7834
摘要： A method of forming an IGFET includes forming a trench in a substrate, forming spacers on opposing sidewalls of the trench, forming a gate insulator on a bottom surface of the trench between the spacers, forming a gate electrode on the gate insulator and the spacers, removing at least portions of the spacers to form voids in the trench after forming the gate electrode, implanting localized source and drain regions through the voids and through the bottom surface of the trench outside the gate electrode, and forming a source and drain in the substrate that include the localized source and drain regions adjacent to the bottom surface of the trench. The localized source and drain regions provide accurately positioned channel junctions beneath the trench. Furthermore, the dopant concentration of the localized source and drain regions is controlled by the amount of the spacers, if any, left intact when the localized source and drain regions are implanted after removing the portions of the spacers.
摘要翻译：形成IGFET的方法包括在衬底中形成沟槽，在沟槽的相对侧壁上形成间隔物，在间隔物之间的沟槽的底表面上形成栅极绝缘体，在栅极绝缘体上形成栅电极和间隔物，在形成栅电极之后移除间隔物的至少部分以在沟槽中形成空隙，通过空隙注入局部源极和漏极区域，并通过栅电极外部的沟槽的底表面，以及在衬底中形成源极和漏极其包括与沟槽的底表面相邻的局部源极和漏极区域。局部源极和漏极区域在沟槽下方提供精确定位的通道结。此外，当在去除间隔物的部分之后植入局部源极和漏极区域时，局部源极和漏极区域的掺杂剂浓度受到间隔物的量（如果有的话）保持不变。

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