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81. 发明授权

US08081666B2 Robust digital communication system 有权
标题翻译：坚固的数字通信系统
公开(公告)号：US08081666B2
公开(公告)日：2011-12-20
申请号：US12371688
申请日：2009-02-16
申请人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
发明人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
IPC分类号： H04J3/04 , H04N7/12
CPC分类号： H04L25/03312 , H03M13/253 , H03M13/256 , H03M13/2732 , H03M13/2936 , H03M13/2957 , H03M13/6331 , H04L1/0041 , H04L1/0047 , H04L1/0054 , H04L1/0057 , H04L1/006 , H04L1/0065 , H04L1/007 , H04L1/0071 , H04L25/03267 , H04L25/03318 , H04L25/063 , H04L25/497 , H04L27/02 , H04L27/066 , H04L2025/03382 , H04N5/04 , H04N5/4401 , H04N5/455 , H04N21/23614 , H04N21/2383 , H04N21/4348 , H04N21/4382
摘要： Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.
摘要翻译：根据第一交错，正常排序的鲁棒VSB数据被重新排序以产生重排序的鲁棒VSB数据。根据第二交错重新排序的稳健VSB数据和ATSC数据被重新排序以产生正常排序的鲁棒VSB数据和重新排序的ATSC数据。通常排序稳健的VSB数据和重新排序的ATSC数据被时分复用以传输到接收机。接收机根据接收机类型或用户选择丢弃重新排序的ATSC数据或正常排序的鲁棒VSB数据。稳健的VSB接收机能够处理在外部解码器上游的正常排序的鲁棒VSB数据，而不会产生交错，从而避免与交织相关联的延迟。

82. 发明授权

US07975204B2 Robust digital communication system 有权
公开(公告)号：US07975204B2
公开(公告)日：2011-07-05
申请号：US11931257
申请日：2007-10-31
申请人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
发明人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
IPC分类号： H03M13/00 , H03M13/03
CPC分类号： H04L25/03312 , H03M13/253 , H03M13/256 , H03M13/2732 , H03M13/2936 , H03M13/2957 , H03M13/6331 , H04L1/0041 , H04L1/0047 , H04L1/0054 , H04L1/0057 , H04L1/006 , H04L1/0065 , H04L1/007 , H04L1/0071 , H04L25/03267 , H04L25/03318 , H04L25/063 , H04L25/497 , H04L27/02 , H04L27/066 , H04L2025/03382 , H04N5/04 , H04N5/4401 , H04N5/455 , H04N21/23614 , H04N21/2383 , H04N21/4348 , H04N21/4382
摘要： Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.

83. 再颁专利

USRE41569E1 Method of processing variable size blocks of data by storing numbers representing size of data blocks in a fifo 有权
标题翻译：通过将表示数据块的大小的数字存储在fifo中来处理可变大小的数据块的方法
公开(公告)号：USRE41569E1
公开(公告)日：2010-08-24
申请号：US12000338
申请日：2007-12-11
申请人： Mark Fimoff , Timothy G. Laud , Ronald B. Lee
发明人： Mark Fimoff , Timothy G. Laud , Ronald B. Lee
IPC分类号： H04L7/00
CPC分类号： H04N19/436 , H04N19/13 , H04N19/423 , H04N19/44 , H04N19/46 , H04N19/91
摘要： A digital data processing system receives compressed variable length encoded digital data in the form of variable length codewords in contiguous variable speed Blocks of data. The boundary signals between adjacent codewords are determined and a demultiplexer sequentially sorts the serial digital data among a plurality of parallelly connected buffers for reducing the bit read speed of the buffers. A corresponding plurality of variable length decoders decodes the data from the buffers and outputs the data in parallel form to a multiplexer where it is reassembled into a serial expanded data stream. The incoming data includes selector information in fixed length headers that are separated, buffered and variable length decoded for controlling the demultiplexer. In one aspect of the invention, the data is sorted into substantially equal sized groups of integral codewords for equalizing the loading of the parallel buffers. In another aspect of the invention, the Block boundary marker signals are processed through much smaller auxiliary buffers using counters to keep track of the Block boundary marker signals for synchronization with the data flowing through the buffers.
摘要翻译：数字数据处理系统以连续的可变速度数据块中的可变长度码字的形式接收压缩的可变长度编码的数字数据。确定相邻码字之间的边界信号，并且解复用器顺序地对多个并联连接的缓冲器中的串行数字数据进行排序，以减小缓冲器的位读取速度。相应的多个可变长度解码器对来自缓冲器的数据进行解码，并且将并行形式的数据输出到多路复用器，并将其重新组合成串行扩展数据流。输入数据包括固定长度报头中的选择器信息，其被分离，缓冲和可变长度解码用于控制解复用器。在本发明的一个方面中，数据被分类成基本相等的大小的整数码字组，用于均衡并行缓冲器的负载。在本发明的另一方面，块边界标记信号通过使用计数器的较小的辅助缓冲器来处理，以跟踪块边界标记信号，以与流过缓冲器的数据同步。

84. 发明授权

US07558297B2 Robust digital communication system 有权
标题翻译：坚固的数字通信系统
公开(公告)号：US07558297B2
公开(公告)日：2009-07-07
申请号：US11931104
申请日：2007-10-31
申请人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
发明人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
IPC分类号： H04J3/04 , H04L5/12 , H03M13/00
CPC分类号： H04L25/03312 , H03M13/253 , H03M13/256 , H03M13/2732 , H03M13/2936 , H03M13/2957 , H03M13/6331 , H04L1/0041 , H04L1/0047 , H04L1/0054 , H04L1/0057 , H04L1/006 , H04L1/0065 , H04L1/007 , H04L1/0071 , H04L25/03267 , H04L25/03318 , H04L25/063 , H04L25/497 , H04L27/02 , H04L27/066 , H04L2025/03382 , H04N5/04 , H04N5/4401 , H04N5/455 , H04N21/23614 , H04N21/2383 , H04N21/4348 , H04N21/4382
摘要： Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.
摘要翻译：根据第一交错，正常排序的鲁棒VSB数据被重新排序以产生重排序的鲁棒VSB数据。根据第二交错重新排序的稳健VSB数据和ATSC数据被重新排序以产生正常排序的鲁棒VSB数据和重新排序的ATSC数据。通常排序稳健的VSB数据和重新排序的ATSC数据被时分复用以传输到接收机。接收机根据接收机类型或用户选择丢弃重新排序的ATSC数据或正常排序的鲁棒VSB数据。稳健的VSB接收机能够处理在外部解码器上游的正常排序的鲁棒VSB数据，而不会产生交错，从而避免与交织相关联的延迟。

85. 发明授权

US07532688B2 Adaptive thresholding algorithm for the noise due to unknown symbols in correlation based channel impulse response (CIR) estimate 有权
标题翻译：在基于相关的信道脉冲响应（CIR）估计中由于未知符号引起的噪声的自适应阈值算法
公开(公告)号：US07532688B2
公开(公告)日：2009-05-12
申请号：US11690560
申请日：2007-03-23
申请人： Mark Fimoff , Sreenivasa M. Nerayanuru , Christopher J. Pladdy
发明人： Mark Fimoff , Sreenivasa M. Nerayanuru , Christopher J. Pladdy
IPC分类号： H04L1/00 , H04L25/08
CPC分类号： H04L25/0218
摘要： An impulse response is estimated for a channel by estimating an intermediate impulse response of the channel. The intermediate impulse response comprises at least one multipath spike and one or more non-deterministic noise components at locations throughout the channel Then, a threshold function is applied to the estimated intermediate impulse response across at least a portion of the channel in order to provide an estimated final impulse response of the channel. The threshold function has the effect of nulling the noise components of the channel having values less than the threshold function at the location within the channel of the respective noise component, and the threshold function is characterized by a level that varies across the portion of the channel from a minimum value to a maximum value in a manner determined by the location of the at least one multipath spike within the channel.
摘要翻译：通过估计信道的中间脉冲响应来估计信道的脉冲响应。中间脉冲响应包括在整个信道的位置处的至少一个多路径尖峰和一个或多个非确定性噪声分量。然后，阈值函数被应用于跨信道的至少一部分的估计的中间脉冲响应，以便提供估计通道的最终脉冲响应。阈值函数具有使在各个噪声分量的信道内的位置处具有小于阈值函数的信道的噪声分量归零的效果，并且阈值函数的特征在于在信道的整个部分上变化的电平以由通道内的至少一个多径峰值的位置确定的方式从最小值到最大值。

86. 发明授权

US07519088B2 Robust digital communication system 有权
公开(公告)号：US07519088B2
公开(公告)日：2009-04-14
申请号：US11076560
申请日：2005-03-09
申请人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
发明人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
IPC分类号： H04J3/04 , H04L5/12 , H03M13/00
CPC分类号： H04L25/03312 , H03M13/253 , H03M13/256 , H03M13/2732 , H03M13/2936 , H03M13/2957 , H03M13/6331 , H04L1/0041 , H04L1/0047 , H04L1/0054 , H04L1/0057 , H04L1/006 , H04L1/0065 , H04L1/007 , H04L1/0071 , H04L25/03267 , H04L25/03318 , H04L25/063 , H04L25/497 , H04L27/02 , H04L27/066 , H04L2025/03382 , H04N5/04 , H04N5/4401 , H04N5/455 , H04N21/23614 , H04N21/2383 , H04N21/4348 , H04N21/4382
摘要： Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.

87. 发明申请

US20090080537A1 ROBUST DIGITAL COMMUNICATION SYSTEM 有权
公开(公告)号：US20090080537A1
公开(公告)日：2009-03-26
申请号：US11931504
申请日：2007-10-31
申请人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
发明人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
IPC分类号： H04N7/12
CPC分类号： H04N21/2383 , H04L1/0057 , H04L1/006 , H04L1/007 , H04L1/0071 , H04L2001/0092 , H04N21/4382
摘要： Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.

88. 发明授权

US07203257B2 Best linear unbiased channel estimation for frequency selective multipath channels with long delay spreads 有权
标题翻译：具有长延迟扩展的频率选择性多径信道的最佳线性无偏信道估计
公开(公告)号：US07203257B2
公开(公告)日：2007-04-10
申请号：US10444338
申请日：2003-05-23
申请人： Mark Fimoff , Sreenivasa M. Nerayanuru , Serdar Ozen , Christopher J. Pladdy , Michael D. Zoltowski
发明人： Mark Fimoff , Sreenivasa M. Nerayanuru , Serdar Ozen , Christopher J. Pladdy , Michael D. Zoltowski
IPC分类号： H03D1/00 , H04L27/06
CPC分类号： H04L25/03292 , H04L25/0212 , H04L25/0224 , H04L25/0244
摘要： A channel impulse response for a channel is determined by determining an initial channel impulse response estimate based upon a stored training sequence and a received signal, by thresholding the initial channel impulse response estimate, by estimating a noise variance for the channel based upon the stored training sequence, the thresholded initial channel impulse response estimate, and the received signal, by determining an inverse of a covariance matrix based on the estimated noise variance and the thresholded initial channel impulse response estimate, by updating the channel impulse response based on the inverse covariance matrix, the stored training sequence, and the received signal, and by thresholding the updated channel impulse response estimate.
摘要翻译：通过基于所存储的训练来估计信道的噪声方差，通过阈值化初始信道脉冲响应估计来确定基于存储的训练序列和接收信号的初始信道脉冲响应估计来确定信道的信道脉冲响应通过基于估计的噪声方差和阈值的初始信道脉冲响应估计来确定协方差矩阵的逆，通过基于逆协方差矩阵更新信道脉冲响应来确定阈值初始信道脉冲响应估计和接收信号，存储的训练序列和接收的信号，以及通过对更新的信道脉冲响应估计进行阈值处理。

89. 发明授权

US07177354B2 Method and apparatus for the control of a decision feedback equalizer 有权
标题翻译：用于控制决策反馈均衡器的方法和装置
公开(公告)号：US07177354B2
公开(公告)日：2007-02-13
申请号：US10421014
申请日：2003-04-22
申请人： Mark Fimoff , William Hillery , Sreenivasa M. Nerayanuru , Serdar Ozen , Christopher J. Pladdy , Michael D. Zoltowski
发明人： Mark Fimoff , William Hillery , Sreenivasa M. Nerayanuru , Serdar Ozen , Christopher J. Pladdy , Michael D. Zoltowski
IPC分类号： H03H7/30 , H03K5/159 , H04N5/00
CPC分类号： H04L25/03063
摘要： The tap weights of an equalizer are initialized in response to a received relatively short training sequence, and new tap weights for the equalizer are thereafter successively calculated in response to relatively long sequences of received symbols and corresponding sequences of decoded symbols. These new tap weights are successively applied to the equalizer.
摘要翻译：响应于接收的相对较短的训练序列来初始化均衡器的抽头权重，然后响应于相对长的接收符号序列和解码符号的相应序列，连续计算均衡器的新抽头加权。这些新的抽头权重被连续应用于均衡器。

90. 发明申请

US20060239342A1 Cir estimating decision feedback equalizer with phase tracker 有权
标题翻译： Cir使用相位跟踪器估计判决反馈均衡器
公开(公告)号：US20060239342A1
公开(公告)日：2006-10-26
申请号：US11114573
申请日：2005-04-26
申请人： Bruno Amizic , Mark Fimoff , Sreenivasa Nerayanuru
发明人： Bruno Amizic , Mark Fimoff , Sreenivasa Nerayanuru
IPC分类号： H03H7/40 , H03K5/159
CPC分类号： H04L25/0212 , H04L25/03057 , H04L25/03203
摘要： An equalizer system includes an equalizer, first and second decoders, and a tap weight controller. The equalizer equalizes a received signal to provide an equalizer output. The first decoder is characterized by a first parallel output, and the first decoder decodes the equalizer output to provide first symbol decisions having a first accuracy. The second decoder is characterized by a second parallel output, the second decoder receives the first parallel output and decodes the equalizer output to provide second symbol decisions having a second accuracy, the first accuracy is greater than the second accuracy, and the second decoder applies the second parallel output to the equalizer. The tap weight controller determines tap weights based on the first symbol decisions and supplies the tap weights to the equalizer.
摘要翻译：均衡器系统包括均衡器，第一和第二解码器以及抽头加权控制器。均衡器对接收到的信号进行均衡以提供均衡器输出。第一解码器的特征在于第一并行输出，并且第一解码器解码均衡器输出以提供具有第一精度的第一符号决定。第二解码器的特征在于第二并行输出，第二解码器接收第一并行输出并解码均衡器输出以提供具有第二精度的第二符号决定，第一精度大于第二精度，第二解码器应用第二并行输出到均衡器。抽头重量控制器基于第一符号决定确定抽头权重，并将抽头权重提供给均衡器。

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