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81. 发明授权

US07235474B1 System and method for imprint lithography to facilitate dual damascene integration with two imprint acts 有权
标题翻译：用于压印光刻的系统和方法，以促进双重镶嵌与两个印记动作的整合
公开(公告)号：US07235474B1
公开(公告)日：2007-06-26
申请号：US10838612
申请日：2004-05-04
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L21/44
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译：提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。

82. 发明申请

US20070082277A1 Process margin using discrete assist features 有权
标题翻译：使用离散辅助功能的处理余量
公开(公告)号：US20070082277A1
公开(公告)日：2007-04-12
申请号：US11245824
申请日：2005-10-07
申请人： Itty Matthew , Bhanwar Singh
发明人： Itty Matthew , Bhanwar Singh
IPC分类号： G03C5/00 , G03F9/00 , G03F1/00
CPC分类号： G03F1/36
摘要： The subject invention provides a system and method for improving the process margin of a lithographic imaging system. The process margin improvement is achieved through the novel placement of discrete assist features and/or the use of forbidden pitches and specific pitch orientations. Novel geometries are utilized, which take advantage of line-end pull back and/or a lack of resolution of pitches perpendicular to an axis of a dipole illumination source. The strategic placement of a series of discrete scatterbar segments on a mask near positions of critical features, such as, for example, contacts, mitigates resist residue that can result from the use of a contiguous scatterbar.
摘要翻译：本发明提供了一种用于改善光刻成像系统的工艺余量的系统和方法。通过新颖的离散辅助特征的放置和/或使用禁止间距和特定的俯仰方向来实现工艺余量的改善。利用新的几何形状，其利用垂直于偶极照明源的轴线的线端拉回和/或缺少分支的分辨率。在临界特征（例如接触）位置附近的掩模上的一系列离散散射片段的战略布置减轻了抵抗可能由于使用连续散射线而产生的残留物。

83. 发明授权

US07158896B1 Real time immersion medium control using scatterometry 失效
标题翻译：实时浸入介质控制采用散射法
公开(公告)号：US07158896B1
公开(公告)日：2007-01-02
申请号：US10978604
申请日：2004-11-01
申请人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
发明人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
IPC分类号： G06F19/00
CPC分类号： G03F7/70916 , G03F7/2041 , G03F7/70341
摘要： Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.
摘要翻译：公开了用于测量和/或控制溶解在浸入式光刻中使用的浸渍介质中的杂质量的系统和/或方法。杂质可以是来自涂覆在基材表面上的光致抗蚀剂层的光致抗蚀剂。已知的光栅结构被构建在衬底上。实时浸没介质监测部件通过利用从已知光栅结构散射的光来便于测量和/或控制溶解在浸没介质中的杂质的量。

84. 发明授权

US07079975B1 Scatterometry and acoustic based active control of thin film deposition process 失效
标题翻译：薄膜沉积工艺的散射和声学主动控制
公开(公告)号：US07079975B1
公开(公告)日：2006-07-18
申请号：US09845231
申请日：2001-04-30
申请人： Arvind Halliyal , Bhanwar Singh , Ramkumar Subramanian
发明人： Arvind Halliyal , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G01B11/02 , G01B15/02
CPC分类号： G01B11/0683 , G01B11/0625 , G01B17/025 , G01N21/47 , G01N21/8422 , G01N21/88 , G01N21/94
摘要： A system for monitoring and controlling the deposition of thin films employed in semiconductor fabrication is provided. The system includes one or more acoustic and/or ultrasonic wave sources, each source directing waves onto one or more thin films deposited on a wafer. Waves reflected from the thin film is collected by a monitoring system, which processes the collected waves. Waves passing through the thin film may similarly be collected by the monitoring system, which processes the collected waves. The collected waves are indicative of the presence of impurities and/or defects in the deposited thin film. The monitoring system analyzes and provides the collected wave data to a processor, which determines whether adjustments to thin film deposition parameters are needed. The system also includes a plurality of thin film deposition devices associated with depositing thin films on the wafer. The processor selectively controls thin film deposition parameters and devices to facilitate regulating deposition.
摘要翻译：提供了用于监测和控制用于半导体制造中的薄膜沉积的系统。该系统包括一个或多个声波和/或超声波波束，每个源将波束引导到沉积在晶片上的一个或多个薄膜上。从薄膜反射的波浪由监测系统收集，监测系统处理收集的波。通过薄膜的波浪可以类似地由监测系统收集，监测系统处理所收集的波。收集的波表示沉积的薄膜中存在杂质和/或缺陷。监测系统分析并将收集的波数据提供给处理器，其确定是否需要对薄膜沉积参数进行调整。该系统还包括与在晶片上沉积薄膜相关联的多个薄膜沉积装置。处理器选择性地控制薄膜沉积参数和装置以便于调节沉积。

85. 发明授权

US07052575B1 System and method for active control of etch process 有权
标题翻译：用于主动控制蚀刻工艺的系统和方法
公开(公告)号：US07052575B1
公开(公告)日：2006-05-30
申请号：US09845454
申请日：2001-04-30
申请人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： C23F1/00
CPC分类号： H01L21/67253 , H01J37/32935 , H01L21/67063 , H01L22/34
摘要： A system for regulating an etch process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the acceptability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor selectively controls the etching devices to regulate etching of the portions of the wafer.
摘要翻译：提供了一种用于调节蚀刻工艺的系统。该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。所收集的光指示在晶片的相应部分处获得的尺寸。测量系统向处理器提供蚀刻相关数据，该处理器确定晶片的相应部分的蚀刻的可接受性。该系统还包括一个或多个蚀刻装置，每个这样的装置对应于晶片的一部分并提供其蚀刻。处理器选择性地控制蚀刻装置来调节晶片的部分的蚀刻。

86. 发明授权

US07001830B2 System and method of pattern recognition and metrology structure for an X-initiative layout design 失效
标题翻译：用于X主动布局设计的模式识别和计量结构的系统和方法
公开(公告)号：US07001830B2
公开(公告)日：2006-02-21
申请号：US10653309
申请日：2003-09-02
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： G03F7/70625 , G03F7/70633 , G03F9/7076 , Y10S438/975
摘要： The present invention relates to inspection methods and systems utilized to provide a best means for inspection of a wafer. The methods and systems include wafer-to-reticle alignment, layer-to-layer alignment and wafer surface feature inspection. The wafer-to-reticle alignment is improved by the addition of diagonal lines to existing alignment marks to decrease the intersection size and corresponding area that a desired point can reside. Layer-to-layer alignment is improved in a similar manner by the addition of oblique and/or non-linear line segments to existing overlay targets. Also, providing for wafer surface inspection in a multitude of desired diagonal axes allows for more accurate feature measurement.
摘要翻译：本发明涉及用于提供用于检查晶片的最佳方法的检查方法和系统。该方法和系统包括晶片到标线片对准，层间对准和晶片表面特征检查。通过将对角线添加到现有的对准标记来减小交叉点大小和期望点可以驻留的对应区域来改善晶片到标线阵列对准。通过向现有覆盖目标添加倾斜和/或非线性线段，以类似的方式改善了层间对齐。此外，在多个所需的对角轴中提供晶片表面检查允许更精确的特征测量。

87. 发明授权

US06972201B1 Using scatterometry to detect and control undercut for ARC with developable BARCs 失效
标题翻译：使用散射法检测和控制ARC的可切割BARC的底切
公开(公告)号：US06972201B1
公开(公告)日：2005-12-06
申请号：US10755794
申请日：2004-01-12
申请人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
发明人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
IPC分类号： G03F7/09 , G03F7/30 , G03F7/38 , H01L21/00 , H01L21/027 , H01L21/66
CPC分类号： G03F7/3028 , G03F7/091 , G03F7/38 , H01L21/0276 , H01L22/12
摘要： Architecture for monitoring a bottom anti-reflective coating (BARC) undercut and residual portions thereof during a development stage using scatterometry. The scatterometry system monitors for BARC undercut and residual BARC material, and if detected, controls the process to minimize such effects in subsequent wafers. If one or more of such effects has exceeded a predetermined limit, the wafer is rerouted for further processing, which can include rework, etch back of the affected layer, or rejection of the wafer, for example.
摘要翻译：用于在使用散射测量的显影阶段期间监测底部抗反射涂层（BARC）底切及其残余部分的结构。散射测量系统监测BARC底切和残留BARC材料，如果检测到，则控制该过程以使后续晶片中的这种影响最小化。如果这种效应中的一个或多个已经超过预定限制，则晶片被重新路由以用于进一步处理，例如，其可以包括返工，受影响层的回蚀或晶片的拒绝。

88. 发明授权

US06931618B1 Feed forward process control using scatterometry for reticle fabrication 有权
标题翻译：使用分光镜制作的散射法进行前馈过程控制
公开(公告)号：US06931618B1
公开(公告)日：2005-08-16
申请号：US10050472
申请日：2002-01-16
申请人： Cyrus E. Tabery , Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Cyrus E. Tabery , Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G01B9/00 , G03F1/00 , G06F17/50 , G03H9/00
CPC分类号： G03F1/84 , G03F1/00
摘要： A system for selectively generating and feeding forward reticle fabrication data is provided. The system includes components for fabricating a reticle and a control system operatively connected to the fabricating components, where the control system can control the operation of the fabricating components. The control system bases its control of the fabricating components, at least in part, on feed forward control information generated by a processor that analyzes scatterometry based reticle fabrication data gathered from measurement components. The scatterometry data is compared to data stored in a signature data store that facilitates analyzing gathered scatterometry signatures to produce feed forward control information that can be employed to manipulate subsequent reticle fabrication processes and/or apparatus.
摘要翻译：提供了一种用于选择性地生成和馈送标线制造数据的系统。该系统包括用于制造掩模版的部件和可操作地连接到制造部件的控制系统，其中控制系统可以控制制造部件的操作。控制系统至少部分地基于由分析从测量部件收集的基于散射仪的掩模版制造数据的处理器生成的前馈控制信息的制造部件的控制。将散射测量数据与存储在签名数据存储器中的数据进行比较，其有助于分析所收集的散射光标签以产生可用于操纵随后的标线制造工艺和/或设备的前馈控制信息。

89. 发明授权

US06912438B2 Using scatterometry to obtain measurements of in circuit structures 失效
标题翻译：使用散射法获得电路结构的测量
公开(公告)号：US06912438B2
公开(公告)日：2005-06-28
申请号：US10277016
申请日：2002-10-21
申请人： Bryan K. Choo , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan
发明人： Bryan K. Choo , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan
IPC分类号： G01N21/47 , H01L21/66 , G06F19/00
CPC分类号： H01L22/20 , G01N21/4738 , H01L2924/0002 , H01L2924/00
摘要： A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.
摘要翻译：公开了用于监测和控制半导体制造工艺的系统和方法。根据基于散射法的技术进行测量，该技术在晶片经历制造过程时在晶片上发生的电路结构中重复。可以采用测量来产生可以用于选择性地调整一个或多个制造部件和/或与其相关联的操作参数以适应制造过程的前馈和/或反馈控制数据。另外，例如，可以基于成本效益分析来确定是否丢弃晶片或其部分的测量。在电路结构中的直接测量减轻了牺牲有价值的芯片的不动产，因为测试光栅结构可能不需要在晶片内形成，并且还有助于对实际影响芯片性能的元件的控制。

90. 发明授权

US06878560B1 Fab correlation system 有权
标题翻译： Fab相关系统
公开(公告)号：US06878560B1
公开(公告)日：2005-04-12
申请号：US10302091
申请日：2002-11-22
申请人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , G05B2219/31457 , G05B2219/32191 , G05B2219/45031 , H01L2924/0002 , H01L2924/00
摘要： A system comprised of a plurality of fabs that are operatively coupled and share data from a common framework for correlating production. The fabs can be coupled via Internet, cellular, optical, landline, microwave and satellite communication means and the like. Data can be transferred to and/or received from a central, integrated correlating entity or from several distributed correlating entities. The fabs send and receive correlating data that relates to production information such as tolerances, critical dimensions, geometry and the like. The correlating entity(s) has the capability to increase production by performing probabilistic computations on the received correlating data and utilizing the resulting information to maintain correlating parameters at remote locations. The computations performed can include such calculations as Bayesian inferencing and the like. The system inherently precludes the necessity for physically transporting parametric test entities between different fab or tooling locations.
摘要翻译：由多个工厂组成的系统，其可操作地耦合并且共享来自公共框架的数据以用于生产。该晶圆厂可以通过互联网，蜂窝，光学，固定电话，微波和卫星通信装置等耦合。可以将数据传送到中央集成的相关实体或从多个分散的相关实体传送到和/或从中央集成的相关实体接收数据。制造厂发送和接收与生产信息相关的相关数据，例如公差，关键尺寸，几何形状等。相关实体具有通过对接收到的相关数据执行概率计算并利用所得到的信息来维持远程位置处的相关参数来增加产量的能力。执行的计算可以包括诸如贝叶斯推理等的计算。该系统固有地排除了在不同晶圆厂或模具位置之间物理传输参数测试实体的必要性。

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