会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 88. 发明申请
    • Sheet Metal Web Stiffener And Chord Nailing Restrictor For Wooden I-Joist
    • 钣金网加固器和和弦钉子限制器木制I-Joist
    • US20070256389A1
    • 2007-11-08
    • US11381441
    • 2006-05-03
    • John Davis
    • John Davis
    • E04C3/30
    • E04C3/18E04B5/12E04C3/125
    • A monolithic sheet metal chord nailing restricting and web stiffening device features a chord plate combined with a web stiffening structure configured for lateral attachment to the web of a wooden I-joist. The chord plate is positioned on the bottom of the web stiffening structure and features a nail restricting hole having a diameter that corresponds to a predetermined diameter of a chord nail as defined by wooden I-joist manufacturers. The web stiffening structure has a web plate for attachment to the web and a buckling opposing web stiffening rib. Once the web stiffening structure is attached to the web above the bearing rest the nail restricting hole restricts chord nailing position and nail shaft diameter to manufacturer defined limits. Two devices may be combined by a web front bridge plate for simultaneous attachment of two opposite devices along an I-joist end.
    • 单片钣金和弦钉子限制和腹板加强装置具有一个弦板,其结合有一个腹板加强结构,用于横向附接到木质I型托梁的腹板。 弦板定位在腹板加强结构的底部,并具有指甲限制孔,其具有对应于由木制I型制造商定义的弦钉的预定直径的直径。 腹板加强结构具有用于连接到腹板的腹板和弯曲的相对腹板加强筋。 一旦腹板加强结构附着在轴承座上方的腹板上,指甲限制孔将弦钉位置和钉轴直径限制在制造商限定的限度内。 两个装置可以通过腹板前桥板组合,用于沿着I型梁端同时附接两个相对的装置。
    • 90. 发明申请
    • CIRCUIT AND METHOD FOR WRITING A BINARY VALUE TO A MEMORY CELL
    • 将二进制值写入存储单元的电路和方法
    • US20060181954A1
    • 2006-08-17
    • US11057281
    • 2005-02-11
    • Paul BunceJohn DavisDonald Plass
    • Paul BunceJohn DavisDonald Plass
    • G11C8/00
    • G11C7/22G11C2207/2263
    • A circuit and a method for writing a binary value to a memory cell are provided. The circuit includes a first field-effect transistor having a first drain, a first drain, and a first gate operably coupled between the first drain and the first source. The first drain is operably coupled to a first memory cell. The first gate configured to receive a first data signal. The circuit further includes a second field-effect transistor having a second drain, a second source, and a second gate operably coupled between the second drain and the second source. The drain source is operably coupled to the first memory cell. The second gate is configured to receive a second data signal. The circuit further includes a first signal inverter having a first input terminal and a first output terminal. The first output terminal is operably coupled to both of the first and second sources. The first signal inverter is configured to output a first control signal on the first output terminal when the first input terminal receives a second control signal. When the first control signal has a second logic level and the first data signal has a first logic level and the second data signal has the second logic level, the first and second field-effect transistors induce the first memory cell to store a first binary value.
    • 提供了一种将二进制值写入存储单元的电路和方法。 电路包括具有第一漏极,第一漏极和第一栅极的第一场效应晶体管,其可操作地耦合在第一漏极和第一源极之间。 第一漏极可操作地耦合到第一存储器单元。 第一门被配置为接收第一数据信号。 电路还包括第二场效应晶体管,其具有可操作地耦合在第二漏极和第二源之间的第二漏极,第二源极和第二栅极。 漏源可操作地耦合到第一存储单元。 第二门被配置为接收第二数据信号。 电路还包括具有第一输入端和第一输出端的第一信号反相器。 第一输出端子可操作地耦合到第一和第二源两者。 第一信号反相器被配置为当第一输入端子接收到第二控制信号时,在第一输出端子上输出第一控制信号。 当第一控制信号具有第二逻辑电平且第一数据信号具有第一逻辑电平且第二数据信号具有第二逻辑电平时,第一和第二场效应晶体管感应第一存储器单元以存储第一二进制值 。