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81. 发明授权

US06763578B2 Method and apparatus for manufacturing known good semiconductor die 失效
标题翻译：用于制造已知的良好半导体管芯的方法和装置
公开(公告)号：US06763578B2
公开(公告)日：2004-07-20
申请号：US08975549
申请日：1997-11-20
申请人： Warren Farnworth , Alan Wood
发明人： Warren Farnworth , Alan Wood
IPC分类号： H05K330
CPC分类号： G01R31/2863 , G01R1/0466 , G01R1/0483 , G01R3/00 , G01R31/2831 , G01R31/2867 , H01L21/6835 , H01L22/20 , H01L23/49816 , H01L24/48 , H01L24/85 , H01L2224/16145 , H01L2224/48463 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H05K3/0058 , H05K3/0067 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/49131 , Y10T29/49144 , Y10T29/49146 , Y10T29/49155 , Y10T29/49764 , H01L2224/78 , H01L2924/00 , H01L2224/45099
摘要： A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed.
摘要翻译：提供了一种用于制造已知的良好半导体晶片的方法和装置。该方法包括以下步骤：测试包含在半导体晶片上的骰子的总功能; 锯切晶片以切割模具; 然后通过组装在具有适于建立管芯上的接合焊盘与外部测试电路之间的电连通的互连的载体中来测试管芯。用于载体的互连可以使用不同的接触技术形成，包括：刚性基板上的厚膜接触构件; 硅衬底上的自限制接触构件; 或具有纹理表面的微型块接触构件。在载体的组装期间，芯片和互连件被光学对准并且被放置成与预定的接触力接触。这就建立了互连上的接触构件和管芯的接合垫之间的电连接。在组装的载体中，管芯和互连件通过包括桥夹，压板和弹簧夹的力分配机构偏压在一起。在对模具进行测试之后，拆下载体并且移除被测试的模具。

82. 发明授权

US5796264A Apparatus for manufacturing known good semiconductor dice 失效
标题翻译：用于制造已知的良好半导体晶片的装置
公开(公告)号：US5796264A
公开(公告)日：1998-08-18
申请号：US823468
申请日：1997-03-19
申请人： Warren Farnworth , Alan Wood
发明人： Warren Farnworth , Alan Wood
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , G01R31/02
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/80 , H01L24/85 , H05K3/4007 , G01R1/06761 , G01R3/00 , G01R31/2831 , G01R31/2863 , H01L2224/16145 , H01L2224/48091 , H01L2224/48463 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01025 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01056 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/30105 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423 , Y10T29/4913 , Y10T29/49144
摘要： A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed.
摘要翻译：提供了一种用于制造已知的良好半导体晶片的方法和装置。该方法包括以下步骤：测试包含在半导体晶片上的骰子的总功能; 锯切晶片以切割模具; 然后通过组装在具有适于建立管芯上的接合焊盘与外部测试电路之间的电连通的互连的载体中来测试管芯。用于载体的互连可以使用不同的接触技术形成，包括：刚性基板上的厚膜接触构件; 硅衬底上的自限制接触构件; 或具有纹理表面的微型块接触构件。在载体的组装期间，芯片和互连件被光学对准并且被放置成与预定的接触力接触。这就建立了互连上的接触构件和管芯的接合垫之间的电连接。在组装的载体中，管芯和互连件通过包括桥夹，压板和弹簧夹的力分配机构偏压在一起。在对模具进行测试之后，拆下载体并且移除被测试的模具。

83. 发明授权

US5640762A Method and apparatus for manufacturing known good semiconductor die 失效
公开(公告)号：US5640762A
公开(公告)日：1997-06-24
申请号：US485086
申请日：1995-06-07
申请人： Warren Farnworth , Alan Wood
发明人： Warren Farnworth , Alan Wood
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/498 , H01L25/10 , H05K3/00 , H05K3/42 , H05K3/30
CPC分类号： G01R31/2863 , G01R1/0466 , G01R1/0483 , H01L21/6835 , H01L22/20 , H01L23/49816 , H01L24/85 , G01R3/00 , G01R31/2831 , G01R31/2867 , H01L2224/16145 , H01L2224/48463 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423 , Y10T29/49126 , Y10T29/49131 , Y10T29/49144 , Y10T29/49146 , Y10T29/49155 , Y10T29/49764
摘要： A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed.

84. 发明授权

US5578526A Method for forming a multi chip module (MCM) 失效
标题翻译：多芯片模块（MCM）的形成方法
公开(公告)号：US5578526A
公开(公告)日：1996-11-26
申请号：US431452
申请日：1995-05-01
申请人： Salman Akram , Warren Farnworth , Alan Wood
发明人： Salman Akram , Warren Farnworth , Alan Wood
IPC分类号： G01R1/04 , G01R31/28 , H01L21/66 , H01L23/13 , H01L23/32 , H01L21/60
CPC分类号： G01R1/04 , G01R31/2863 , H01L22/22 , H01L23/13 , H01L23/32 , H01L2224/16145 , H01L2224/48227 , H01L2924/09701 , H01L2924/10253
摘要： A method for forming a multi chip module for singulated semiconductor dice or dice contained on a wafer is provided. The method includes forming an interconnect adapted to support and establish an electrical connection with the dice. The interconnect includes a substrate formed of a material such as silicon with raised contact members. The raised contact members include projections adapted to penetrate contact locations on the dice (e.g., bond pads) to a limited penetration depth to establish the electrical connection. A conductive layer and conductive traces are formed on the substrate to form an electrical path to the contact members. Programmable links, such as fuses or anti-fuses, can be included in the electrical path for enabling or disabling select dice of the module. A packaged multi chip module assembly can be formed by encapsulation of the dice and substrate in an insulating material or by forming a ceramic base and cover.
摘要翻译：提供一种用于形成包含在晶片上的单片半导体晶片或骰子的多芯片模块的方法。该方法包括形成适于支撑并建立与骰子的电连接的互连。互连包括由诸如具有凸起接触构件的硅的材料形成的衬底。凸起的接触构件包括适于将骰子（例如，接合垫）上的接触位置穿透到有限的穿透深度以建立电连接的突起。导电层和导电迹线形成在衬底上以形成到接触构件的电路径。可编程链路，如保险丝或反熔丝，可以包含在电气路径中，用于启用或禁用模块的选择骰子。封装的多芯片模块组件可以通过将骰子和基板封装在绝缘材料中或通过形成陶瓷基底和盖而形成。

85. 发明申请

US20080042247A1 Stacked Semiconductor Components With Through Wire Interconnects (TWI) 有权
标题翻译：具有直通线互连的叠层半导体元件（TWI）
公开(公告)号：US20080042247A1
公开(公告)日：2008-02-21
申请号：US11859776
申请日：2007-09-23
申请人： Alan Wood , David Hembree
发明人： Alan Wood , David Hembree
IPC分类号： H01L23/495
CPC分类号： H01L23/02 , B33Y70/00 , H01L21/6835 , H01L23/3114 , H01L23/48 , H01L23/481 , H01L23/49827 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2221/6834 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/0401 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13024 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/4554 , H01L2224/45565 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/4824 , H01L2224/48471 , H01L2224/48475 , H01L2224/48599 , H01L2224/48699 , H01L2224/48992 , H01L2224/49429 , H01L2224/78301 , H01L2224/85001 , H01L2224/85045 , H01L2224/85051 , H01L2224/85121 , H01L2224/85205 , H01L2224/85444 , H01L2224/85951 , H01L2225/06506 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06596 , H01L2924/00015 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19042 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2224/45144 , H01L2224/45147 , H01L2224/45644 , H01L2924/00 , H01L2924/2075 , H01L2924/013 , H01L2924/00013 , H01L2924/00012
摘要： A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.
摘要翻译：半导体部件包括具有基板接触的半导体基板和与该基板接触部接合的贯通线互连（TWI）。通线互连（TWI）包括通过基板接触和基板的通孔，连接到基板触点的通孔中的导线和线上的触点。堆叠的半导体部件包括半导体衬底和堆叠在衬底上并结合到衬底上的通孔互连的第二半导体衬底。一种用于制造具有通孔布线的半导体部件的方法包括以下步骤：提供具有基板接触的半导体基板，通过基板接触形成通孔，并且部分地穿过基板，将导线放置在通孔中，将导线接合到衬底接触，然后从第二侧使衬底变薄以暴露线上的接触。用于制造半导体部件的系统包括被配置为将导线放置在通路中并且在导线和基板接触之间形成接合连接的接合毛细管。

86. 发明申请

US20070126091A1 Semiconductor components having through wire interconnects (TWI) 有权
公开(公告)号：US20070126091A1
公开(公告)日：2007-06-07
申请号：US11296057
申请日：2005-12-07
申请人： Alan Wood , David Hembree
发明人： Alan Wood , David Hembree
IPC分类号： H01L23/495
CPC分类号： H01L23/02 , B33Y70/00 , H01L21/6835 , H01L23/3114 , H01L23/48 , H01L23/481 , H01L23/49827 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2221/6834 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/0401 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13024 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/4554 , H01L2224/45565 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/4824 , H01L2224/48471 , H01L2224/48475 , H01L2224/48599 , H01L2224/48699 , H01L2224/48992 , H01L2224/49429 , H01L2224/78301 , H01L2224/85001 , H01L2224/85045 , H01L2224/85051 , H01L2224/85121 , H01L2224/85205 , H01L2224/85444 , H01L2224/85951 , H01L2225/06506 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06596 , H01L2924/00015 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19042 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2224/45144 , H01L2224/45147 , H01L2224/45644 , H01L2924/00 , H01L2924/2075 , H01L2924/013 , H01L2924/00013 , H01L2924/00012
摘要： A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.

87. 发明申请

US20070167000A1 Methods and systems for fabricating semiconductor components with through wire interconnects (TWI) 有权
标题翻译：通过导线互连（TWI）制造半导体元件的方法和系统
公开(公告)号：US20070167000A1
公开(公告)日：2007-07-19
申请号：US11712815
申请日：2007-03-01
申请人： Alan Wood , David Hembree
发明人： Alan Wood , David Hembree
IPC分类号： H01L21/4763
CPC分类号： H01L23/02 , B33Y70/00 , H01L21/6835 , H01L23/3114 , H01L23/48 , H01L23/481 , H01L23/49827 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2221/6834 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/0401 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13024 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/4554 , H01L2224/45565 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/4824 , H01L2224/48471 , H01L2224/48475 , H01L2224/48599 , H01L2224/48699 , H01L2224/48992 , H01L2224/49429 , H01L2224/78301 , H01L2224/85001 , H01L2224/85045 , H01L2224/85051 , H01L2224/85121 , H01L2224/85205 , H01L2224/85444 , H01L2224/85951 , H01L2225/06506 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06596 , H01L2924/00015 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19042 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2224/45144 , H01L2224/45147 , H01L2224/45644 , H01L2924/00 , H01L2924/2075 , H01L2924/013 , H01L2924/00013 , H01L2924/00012
摘要： A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.
摘要翻译：半导体部件包括具有基板接触的半导体基板和与该基板接触部接合的贯通线互连（TWI）。通线互连（TWI）包括通过基板接触和基板的通孔，连接到基板触点的通孔中的导线和线上的触点。堆叠的半导体部件包括半导体衬底和堆叠在衬底上并结合到衬底上的通孔互连的第二半导体衬底。一种用于制造具有通孔布线的半导体部件的方法包括以下步骤：提供具有基板接触的半导体基板，通过基板接触形成通孔，并且部分地穿过基板，将导线放置在通孔中，将导线接合到衬底接触，然后从第二侧使衬底变薄以暴露线上的接触。用于制造半导体部件的系统包括被配置为将导线放置在通路中并且在导线和基板接触之间形成接合连接的接合毛细管。

88. 发明申请

US20050084986A1 Semiconductor test board having laser patterned conductors 失效
标题翻译：具有激光图案导体的半导体测试板
公开(公告)号：US20050084986A1
公开(公告)日：2005-04-21
申请号：US10983111
申请日：2004-11-05
申请人： David Hembree , Alan Wood
发明人： David Hembree , Alan Wood
IPC分类号： H01L21/66 , H01L21/00
CPC分类号： H01L22/20 , H01L2224/05001 , H01L2224/05022 , H01L2224/05548 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/0568 , H01L2224/05681 , H01L2224/05684 , H01L2224/16 , H01L2924/00014 , H01L2924/01087 , H01L2924/014 , H01L2224/05099 , H01L2924/013
摘要： A method for fabricating semiconductor components is performed using a laser scanner and a laser imaging process. A substrate, such as a semiconductor wafer, containing multiple semiconductor components, such as dice or packages, is provided. The components include integrated circuits, and component contacts in electrical communication with the integrated circuits. Initially, the components are tested to identify and locate good components and defective components on the substrate. Using data from the testing step and the laser scanner, patterns of conductors are then formed to either repair the defective components, to electrically isolate the defective components for burn-in, or to form component clusters containing only the good components. Alternately, using data from the testing step and the laser scanner, a matching test board can be fabricated, and used to electrically engage the good components, while the defective components remain isolated.
摘要翻译：使用激光扫描仪和激光成像处理来执行制造半导体部件的方法。提供了诸如骰子或包装之类的诸如半导体晶片的衬底，其包含多个半导体元件。这些部件包括集成电路和与集成电路进行电气通信的部件触点。最初，对组件进行测试以识别和定位衬底上的良好组件和缺陷组件。使用来自测试步骤和激光扫描仪的数据，然后形成导体图案，以修复有缺陷的部件，将缺陷部件电隔离以进行老化，或形成仅包含良好部件的组件簇。或者，使用来自测试步骤和激光扫描仪的数据，可以制造匹配的测试板，并且用于电气接合良好部件，同时有缺陷的部件保持隔离。

89. 发明申请

US20070246819A1 Semiconductor components and systems having encapsulated through wire interconnects (TWI) and wafer level methods of fabrication 有权
标题翻译：半导体元件和系统已通过电线互连（TWI）和晶圆级制造方法封装
公开(公告)号：US20070246819A1
公开(公告)日：2007-10-25
申请号：US11409638
申请日：2006-04-24
申请人： David Hembree , Alan Wood
发明人： David Hembree , Alan Wood
IPC分类号： H01L23/04
CPC分类号： H01L24/16 , G01R1/06716 , G01R1/07307 , H01L21/486 , H01L21/565 , H01L21/568 , H01L21/76877 , H01L21/76885 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/81 , H01L24/85 , H01L25/0657 , H01L25/105 , H01L2224/02125 , H01L2224/0233 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/02373 , H01L2224/02375 , H01L2224/0333 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05548 , H01L2224/05552 , H01L2224/05554 , H01L2224/05555 , H01L2224/05567 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/1134 , H01L2224/13009 , H01L2224/13024 , H01L2224/13082 , H01L2224/131 , H01L2224/16146 , H01L2224/45014 , H01L2224/45015 , H01L2224/451 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45572 , H01L2224/45639 , H01L2224/45644 , H01L2224/45655 , H01L2224/45684 , H01L2224/45698 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48455 , H01L2224/48463 , H01L2224/4847 , H01L2224/48471 , H01L2224/48475 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/4899 , H01L2224/48992 , H01L2224/78301 , H01L2224/85051 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85951 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/1058 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/07811 , H01L2924/10155 , H01L2924/10161 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/181 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2224/45164 , H01L2924/013 , H01L2924/00013
摘要： A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked-systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.
摘要翻译：半导体部件包括具有衬底接触的半导体衬底和附着到衬底触点的通线互连（TWI）。通线互连提供了在半导体衬底的相对的第一和第二侧上具有触点的多电平互连。通线互连（TWI）包括穿过基板触点和基板的通孔，通孔中的导线与基板接触具有接合连接，接近第一侧的导线上的第一触点和第二触点电线靠近第二侧。通线互连（TWI）还包括聚合物层，其部分地封装通孔互连（TWI），同时使第一触点暴露。半导体组件可用于制造堆叠系统，模块系统和测试系统。制造半导体部件的方法可以包括用于形成聚合物层的膜辅助成型工艺。

90. 发明授权

US10107421B2 Pipe 有权
公开(公告)号：US10107421B2
公开(公告)日：2018-10-23
申请号：US13983598
申请日：2012-02-07
申请人： Alan Wood , Horst Sandner
发明人： Alan Wood , Horst Sandner
IPC分类号： F16L9/12 , B29C71/00 , C08J5/00 , F16L11/06 , E21B17/01 , B29C47/00 , B29C47/90 , B29C71/02 , B29K71/00 , B29C47/88
摘要： A polyetheretherketone pipe of length greater than 250 meters and a residual stress of less than 5 MPa may be made using a calibrator device (2) which includes a cone shaped opening (6) arranged to receive a molten extruded pipe shaped polymer. Attached to the front member (4) is a vacuum plate (14a) and successive vacuum plates (14b-14h) are attached to one another to define an array of vacuum plates, the vacuum plates being arranged to allow a vacuum to be applied to a pipe precursor passing through opening (16). The vacuum plates (14) also include (10) temperature control means for heating or cooling the plates and therefore heating or cooling a pipe precursor passing through the openings. With a vacuum applied to opening (6, 16) and heating/cooling the plates, an extruded hot plastics pipe is inserted into calibrator (2) via opening (6) and conveyed through opening (16) in plates (14), whereupon it is urged by the vacuum against the cylindrical surface defined by plates (14) to maintain its shape and the (15) temperature of each plate is controlled to control the rate of cooling of the pipe precursor passing through. The pipe may be cooled at a relatively slow rate so that a pipe made from a relatively fast crystallizing polymer crystallizes and the crystallinity of the pipe along its extent and throughout its thickness is substantially constant.

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