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81. 发明授权

US5747869A Reduced pitch laser redundancy fuse bank structure 失效
公开(公告)号：US5747869A
公开(公告)日：1998-05-05
申请号：US831389
申请日：1997-04-01
申请人： Kirk Prall , Tod S. Stone , Paul S. Zagar
发明人： Kirk Prall , Tod S. Stone , Paul S. Zagar
IPC分类号： H01L21/82 , G11C29/00 , H01L23/525 , H01L27/10 , H01L29/00
CPC分类号： G11C29/785 , G11C29/80 , H01L23/5258 , H01L2924/0002
摘要： A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added to a standard laser fuse structure such that it intersects the fuses and the number of available fuses is doubled.

82. 发明授权

US5597746A Method of forming field effect transistors relative to a semiconductor substrate and field effect transistors produced according to the method 失效
标题翻译：根据该方法制造相对于半导体衬底的场效应晶体管和场效应晶体管的方法
公开(公告)号：US5597746A
公开(公告)日：1997-01-28
申请号：US512804
申请日：1995-08-09
申请人： Kirk Prall
发明人： Kirk Prall
IPC分类号： H01L21/336 , H01L21/60 , H01L21/768 , H01L21/265
CPC分类号： H01L21/76897 , H01L21/76816 , H01L21/76831 , H01L21/76879 , H01L29/41783 , H01L29/66575 , H01L29/6659 , H01L29/66628
摘要： A method of forming a field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expanse of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in place, etching the first gate block selectively relative to the insulating dielectric layer to define the transistor gate having a second lateral expanse adjacent the substrate which is equal to the resultant lateral expanse; and g) providing a conductivity enhancing impurity into the substrate adjacent the transistor gate. The invention has particular utility in fabrication of field effect transistors having an elevated source and an elevated drain. The invention also contemplates products produced by the above process.
摘要翻译：一种形成相对于半导体衬底的场效应晶体管的方法，其中晶体管具有限定其下面形成的半导体材料的横向宽度的栅极，用于提供晶体管沟道区，其包括：a）在半导体衬底上提供导电栅极层 ; b）将所述导电栅层图案化成第一栅极块，所述第一栅极块具有大于所产生的横向扩展的第一横向延伸; c）在所述第一栅极块上提供绝缘介电层; d）在第一栅极块和绝缘电介质层上提供光致抗蚀剂的图案化层，所述图案化光致抗蚀剂包括位于第一栅极块的第一横向扩展部之上和之内的光致抗蚀剂阻挡层; e）使图案化的光致抗蚀剂在适当位置，相对于第一栅极块选择性地蚀刻绝缘介电层; f）在蚀刻绝缘电介质层和图案化的光致抗蚀剂就位之后，相对于绝缘电介质层选择性地蚀刻第一栅极块以限定晶体管栅极，其具有与基板相邻的第二横向宽度，其等于所得到的横向宽度; 和g）在与晶体管栅极相邻的衬底中提供增强电导率的杂质。本发明在具有升高的源极和升高的漏极的场效应晶体管的制造中具有特别的用途。本发明还考虑了通过上述方法生产的产品。

83. 发明授权

US5387534A Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells 失效
标题翻译：形成非挥发性声纳存储器单元阵列和非突发性声纳存储器单元阵列的方法
公开(公告)号：US5387534A
公开(公告)日：1995-02-07
申请号：US238474
申请日：1994-05-05
申请人： Kirk Prall
发明人： Kirk Prall
IPC分类号： H01L21/8247 , H01L21/70
CPC分类号： H01L27/11521
摘要： An array of SONOS memory cells includes: a) a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; b) a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; c) a word line commonly interconnecting the adjacent SONOS gates of the pair; and d) separate bit lines separately electrically engaging the separated diffusion regions of the pair. LDD regions are also included. A method of producing such a construction is disclosed.
摘要翻译： SONOS存储单元的阵列包括：a）在阵列区域内的硅衬底顶上的一对间隔相邻的SONOS门; b）栅极之间的沟槽，沟槽具有相对的向下细长的侧壁和基部，该侧壁掺杂有第一导电类型的导电性增强杂质，以在第二导电类型的相应栅极之间和之间相邻限定分离的源极/漏极扩散区域沟槽填充有有效的电绝缘材料; c）通常将该对的相邻SONOS门互连的字线; 以及d）分开地将所述对的分离的扩散区域电连接的位线分开。也包括LDD区域。公开了一种制造这种结构的方法。

84. 发明申请

US20120132979A1 Memory Devices And Methods Of Forming Memory Devices 有权
标题翻译：存储器件和形成存储器件的方法
公开(公告)号：US20120132979A1
公开(公告)日：2012-05-31
申请号：US13365472
申请日：2012-02-03
申请人： Kirk Prall , Behnam Moradi , Seiichi Aritome , Di Li , Chris Larsen
发明人： Kirk Prall , Behnam Moradi , Seiichi Aritome , Di Li , Chris Larsen
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/66825 , H01L21/22 , H01L21/265 , H01L21/26506 , H01L21/324 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/6659 , H01L29/66659 , H01L29/788
摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
摘要翻译：公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中线结构。

85. 发明授权

US07911837B2 Multi-state memory cell with asymmetric charge trapping 有权
标题翻译：具有不对称电荷捕获的多状态存储单元
公开(公告)号：US07911837B2
公开(公告)日：2011-03-22
申请号：US12581674
申请日：2009-10-19
申请人： Kirk Prall
发明人： Kirk Prall
IPC分类号： G11C11/34
CPC分类号： H01L29/7887 , H01L29/7923
摘要： A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.
摘要翻译：多态NAND存储单元由衬底中的两个漏极/源极区域组成。在漏极/源极区域之间的衬底上方形成氧化物 - 氮化物 - 氧化物结构。用作不对称电荷捕获层的氮化物层。控制栅极位于氧化物 - 氮化物 - 氧化物结构之上。在漏极/源极区域上的不对称偏置导致具有较高电压的漏极/源极区域通过栅极感应漏极漏极注入到基本上邻近该漏极/源极区域的俘获层而注入不对称分布孔。

86. 发明申请

US20110013463A1 Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes 有权
标题翻译：通过执行卤素离子注入和扩散过程形成存储器件的方法
公开(公告)号：US20110013463A1
公开(公告)日：2011-01-20
申请号：US12892691
申请日：2010-09-28
申请人： Kirk Prall , Behnam Moradi , Seiichi Aritome , Di Li , Chris Larsen
发明人： Kirk Prall , Behnam Moradi , Seiichi Aritome , Di Li , Chris Larsen
IPC分类号： G11C11/34
CPC分类号： H01L29/66825 , H01L21/22 , H01L21/265 , H01L21/26506 , H01L21/324 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/6659 , H01L29/66659 , H01L29/788
摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
摘要翻译：公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中线结构。

87. 发明授权

US07569468B2 Method for forming a floating gate memory with polysilicon local interconnects 失效
标题翻译：用于形成具有多晶硅局部互连的浮动栅极存储器的方法
公开(公告)号：US07569468B2
公开(公告)日：2009-08-04
申请号：US11217624
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/3205
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

88. 发明授权

US07485528B2 Method of forming memory devices by performing halogen ion implantation and diffusion processes 有权
标题翻译：通过卤素离子注入和扩散工艺形成存储器件的方法
公开(公告)号：US07485528B2
公开(公告)日：2009-02-03
申请号：US11457620
申请日：2006-07-14
申请人： Kirk Prall , Behnam Moradi , Seiichi Aritome , Di Li , Chris Larsen
发明人： Kirk Prall , Behnam Moradi , Seiichi Aritome , Di Li , Chris Larsen
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/22 , H01L21/265 , H01L21/26506 , H01L21/324 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/6659 , H01L29/66659 , H01L29/788
摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
摘要翻译：公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中线结构。

89. 发明申请

US20090010075A9 NROM memory cell, memory array, related devices and methods 有权
公开(公告)号：US20090010075A9
公开(公告)日：2009-01-08
申请号：US11346413
申请日：2006-02-02
申请人： Kirk Prall , Leonard Forbes
发明人： Kirk Prall , Leonard Forbes
IPC分类号： G11C16/04
CPC分类号： H01L29/7926 , G11C11/5692 , G11C16/0466 , G11C16/0475 , H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7923
摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

90. 发明申请

US20070111443A1 Memory transistor and methods 有权
标题翻译：存储晶体管及方法
公开(公告)号：US20070111443A1
公开(公告)日：2007-05-17
申请号：US11648200
申请日：2006-12-29
申请人： Kirk Prall
发明人： Kirk Prall
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/28273 , H01L21/28282 , H01L29/66643 , H01L29/7839 , H01L29/7885 , H01L29/792
摘要： A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.
摘要翻译：形成存储晶体管的方法包括提供包括半导体材料并形成间隔开的源极/漏极结构的衬底。源极/漏极结构中的至少一个与半导体材料形成肖特基接触。该方法还包括在间隔开的源极/漏极结构之间形成存储栅极，并形成可操作地设置在存储器栅极上的控制栅极。

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