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81. 发明授权

US08227874B2 Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes 有权
标题翻译：具有高K栅极电介质层和金属栅电极的半导体晶体管
公开(公告)号：US08227874B2
公开(公告)日：2012-07-24
申请号：US12861913
申请日：2010-08-24
申请人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
发明人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
IPC分类号： H01L29/78
CPC分类号： H01L29/1037 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.
摘要翻译：半导体结构。半导体结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）最终栅极电介质区，（iv）最终栅电极区和（v）第一栅介质角区域。最后的栅介质区域（i）包括第一电介质材料，和（ii）设置在沟道区域和最终栅电极区域之间并与其直接物理接触。第一栅介质角区域（i）包括与第一介电材料不同的第二电介质材料，（ii）设置在第一源极/漏极区域和最终栅极电介质区域之间并与之直接物理接触;（iii））不与最终栅电极区域直接物理接触，并且（iv）在参考方向上与最终栅电极区域重叠。

82. 发明授权

US08193563B2 High power device isolation and integration 有权
标题翻译：大功率器件隔离和集成
公开(公告)号：US08193563B2
公开(公告)日：2012-06-05
申请号：US12768877
申请日：2010-04-28
申请人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
发明人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
IPC分类号： H01L29/66
CPC分类号： H01L21/76229 , H01L21/76232 , H01L21/823481 , H01L21/84 , H01L27/088 , H01L29/0653 , H01L29/0878 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7824 , H01L29/7835
摘要： A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.
摘要翻译：一种制造结构的结构和方法。所述结构包括：在半导体衬底中的介电隔离，所述电介质隔离部在垂直于所述衬底的顶表面的方向上延伸到所述衬底中的第一距离，围绕所述衬底的第一区域和所述第二区域的介电隔离，介质隔离的顶表面与基底的顶表面共面; 在所述基板的所述第二区域中的介电区域; 所述电介质区域沿垂直方向延伸到所述衬底中第二距离，所述第一距离大于所述第二距离; 以及第一区域中的第一器件和第二区域中的第二器件，所述第一器件不同于所述第二器件，所述电介质区域将所述第二器件的第一元件与所述第二器件的第二元件隔离。

83. 发明授权

US08110875B2 Structure for charge dissipation during fabrication of integrated circuits and isolation thereof 有权
标题翻译：集成电路制造过程中电荷耗散的结构及其分离
公开(公告)号：US08110875B2
公开(公告)日：2012-02-07
申请号：US12166362
申请日：2008-07-02
申请人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
发明人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Timothy Dooling Sullivan , Steven Howard Voldman
IPC分类号： H01L23/62
CPC分类号： H01L27/0248 , Y10S438/926
摘要： A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
摘要翻译：用于在集成电路制造期间耗散电荷的结构。该结构包括：半导体衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

84. 发明授权

US07781292B2 High power device isolation and integration 有权
标题翻译：大功率器件隔离和集成
公开(公告)号：US07781292B2
公开(公告)日：2010-08-24
申请号：US11741889
申请日：2007-04-30
申请人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
发明人： Jeffrey Peter Gambino , Steven Howard Voldman , Michael Joseph Zierak
IPC分类号： H01L21/336
CPC分类号： H01L21/76229 , H01L21/76232 , H01L21/823481 , H01L21/84 , H01L27/088 , H01L29/0653 , H01L29/0878 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7824 , H01L29/7835
摘要： A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.
摘要翻译：一种制造结构的结构和方法。所述结构包括：在半导体衬底中的介电隔离，所述电介质隔离部在垂直于所述衬底的顶表面的方向上延伸到所述衬底中的第一距离，围绕所述衬底的第一区域和所述第二区域的介电隔离，介质隔离的顶表面与基底的顶表面共面; 在所述基板的所述第二区域中的介电区域; 所述电介质区域沿垂直方向延伸到所述衬底中第二距离，所述第一距离大于所述第二距离; 以及第一区域中的第一器件和第二区域中的第二器件，所述第一器件不同于所述第二器件，所述电介质区域将所述第二器件的第一元件与所述第二器件的第二元件隔离。

85. 发明授权

US07781267B2 Enclosed nanotube structure and method for forming 失效
标题翻译：封闭纳米管结构和形成方法
公开(公告)号：US07781267B2
公开(公告)日：2010-08-24
申请号：US11419329
申请日：2006-05-19
申请人： Jeffrey Peter Gambino , Son Van Nguyen
发明人： Jeffrey Peter Gambino , Son Van Nguyen
IPC分类号： H01L21/82
CPC分类号： B82Y10/00 , G11C13/025 , H01L21/7682 , H01L29/0665 , H01L29/685 , H01L29/86 , H01L51/0048 , H01L51/0554 , H01L2221/1094
摘要： A semiconductor device and associated method for forming. The semiconductor device comprises an electrically conductive nanotube formed over a first electrically conductive member such that a first gap exists between a bottom side the electrically conductive nanotube and a top side of the first electrically conductive member. A second insulating layer is formed over the electrically conductive nanotube. A second gap exists between a top side of the electrically conductive nanotube and a first portion of the second insulating layer. A first via opening and a second via opening each extend through the second insulating layer and into the second gap.
摘要翻译：一种半导体器件及相关的成型方法。半导体器件包括形成在第一导电构件上的导电纳米管，使得第一间隙存在于导电纳米管的底侧和第一导电构件的顶侧之间。在导电性纳米管上形成第二绝缘层。在导电纳米管的顶侧和第二绝缘层的第一部分之间存在第二间隙。第一通孔开口和第二通孔开口各自延伸穿过第二绝缘层并进入第二间隙。

86. 发明申请

US20090212376A1 SEMICONDUCTOR TRANSISTORS HAVING HIGH-K GATE DIELECTRIC LAYERS AND METAL GATE ELECTRODES 失效
标题翻译：具有高K栅电介质层和金属栅极电极的半导体晶体管
公开(公告)号：US20090212376A1
公开(公告)日：2009-08-27
申请号：US12038195
申请日：2008-02-27
申请人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
发明人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/1037 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.
摘要翻译：半导体结构及其形成方法。半导体结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）最终栅极电介质区，（iv）最终栅电极区和（v）第一栅介质角区域。最后的栅介质区域（i）包括第一电介质材料，和（ii）设置在沟道区域和最终栅电极区域之间并与其直接物理接触。第一栅介质角区域（i）包括与第一介电材料不同的第二电介质材料，（ii）设置在第一源极/漏极区域和最终栅极电介质区域之间并与之直接物理接触;（iii））不与最终栅电极区域直接物理接触，并且（iv）在参考方向上与最终栅电极区域重叠。

87. 发明申请

US20090127619A1 DEEP TRENCH SEMICONDUCTOR STRUCTURE AND METHOD 有权
标题翻译： DEEP TRENCH SEMICONDUCTOR结构与方法
公开(公告)号：US20090127619A1
公开(公告)日：2009-05-21
申请号：US11942756
申请日：2007-11-20
申请人： Jeffrey Peter Gambino , Benjamin Thomas Voegeli , Steven Howard Voldman , Michael Joseph Zierak
发明人： Jeffrey Peter Gambino , Benjamin Thomas Voegeli , Steven Howard Voldman , Michael Joseph Zierak
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823437 , H01L21/823828 , H01L29/1037 , H01L29/4236 , H01L29/66621 , H01L29/66787
摘要： An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.
摘要翻译：一种电气结构和成型方法。电结构包括半导体衬底，其包括深沟槽，在深沟槽的外表面上形成氧化物衬层，以及形成在半导体衬底内的场效应晶体管（FET）。第一FET包括源极结构，漏极结构和栅极结构。栅极结构包括连接到多晶硅填充结构的栅极触点。多晶硅填充结构形成在氧化物衬垫层之上和深沟槽内。多晶硅填充结构被配置为横向跨越多晶硅填充结构流动电流，使得电流平行于半导体衬底的顶表面流动。

88. 发明申请

US20080272398A1 CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING 有权
标题翻译：用于半导体器件的导电间隔件和形成方法
公开(公告)号：US20080272398A1
公开(公告)日：2008-11-06
申请号：US11848597
申请日：2007-08-31
申请人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
发明人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
IPC分类号： H01L29/00
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译：一种在半导体器件上形成导电间隔物的方法。该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层。任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

89. 发明授权

US06548357B2 Modified gate processing for optimized definition of array and logic devices on same chip 失效
标题翻译：改进的门处理，用于在同一芯片上优化阵列和逻辑器件的定义
公开(公告)号：US06548357B2
公开(公告)日：2003-04-15
申请号：US10117869
申请日：2002-04-08
申请人： Mary E. Weybright , Gary Bronner , Richard A. Conti , Ramachandra Divakaruni , Jeffrey Peter Gambino , Peter Hoh , Uwe Schroeder
发明人： Mary E. Weybright , Gary Bronner , Richard A. Conti , Ramachandra Divakaruni , Jeffrey Peter Gambino , Peter Hoh , Uwe Schroeder
IPC分类号： H01L21336
CPC分类号： H01L27/10894 , H01L21/76897 , H01L21/823456 , H01L27/1052 , H01L27/10873
摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.
摘要翻译：在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。这扩大了阵列栅极导体处理窗口。第二电介质盖层改善了支撑装置和阵列装置的线宽控制。在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

90. 发明授权

US06200834B1 Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (CMP) planarization 失效
标题翻译：使用多晶硅掩模和化学机械抛光（CMP）平面化制造两种不同栅介质厚度的工艺
公开(公告)号：US06200834B1
公开(公告)日：2001-03-13
申请号：US09359290
申请日：1999-07-22
申请人： Gary B. Bronner , Jeffrey Peter Gambino , Carl J. Radens
发明人： Gary B. Bronner , Jeffrey Peter Gambino , Carl J. Radens
IPC分类号： H01L21335
CPC分类号： H01L21/823443 , H01L21/82345 , H01L21/823462
摘要： A method of forming a semiconductor device, including forming a substrate with a memory array region and a logic device region, growing a thick gate dielectric over the substrate, forming a gate stack, including a first polysilicon layer, over the thick gate dielectric for the memory array region, forming a thin gate dielectric on the substrate over the logic device region, wherein layers of the gate stack in the memory array region protect the thick gate oxide during the forming of the thin gate dielectric, forming a second polysilicon layer for the gate stack in the logic device region, to produce a resulting structure, wherein a thickness of the second polysilicon layer is at least as thick as the gate stack in the memory array region, planarizing the structure using chemical mechanical polishing (CMP), and patterning the gate stacks in said memory array region and the logic device region.
摘要翻译：一种形成半导体器件的方法，包括形成具有存储器阵列区域和逻辑器件区域的衬底，在衬底上生长厚栅极电介质，在厚栅极电介质上形成包括第一多晶硅层的栅极堆叠，用于存储器阵列区域，在逻辑器件区域上在衬底上形成薄栅极电介质，其中存储器阵列区域中的栅极堆叠层在形成薄栅极电介质期间保护厚栅极氧化物，形成第二多晶硅层，用于栅堆叠在逻辑器件区域中，以产生所得结构，其中第二多晶硅层的厚度至少与存储器阵列区域中的栅极堆叠一样厚，使用化学机械抛光（CMP）平坦化结构，并且图案化所述存储器阵列区域和逻辑器件区域中的栅极堆叠。

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