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81. 发明申请

US20090121260A1 DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS 有权
标题翻译：双面集成电路板
公开(公告)号：US20090121260A1
公开(公告)日：2009-05-14
申请号：US11939612
申请日：2007-11-14
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/78
CPC分类号： G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译：双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。下晶片可以包括布线水平。下部晶片可以包括用于触点的着陆焊盘。与下晶片的硅层的接触可以被硅化。

82. 发明申请

US20080303139A1 CHIP-IN-SLOT INTERCONNECT FOR 3D CHIP STACKS 失效
标题翻译：用于3D芯片堆叠的插槽插槽互连
公开(公告)号：US20080303139A1
公开(公告)日：2008-12-11
申请号：US11759651
申请日：2007-06-07
申请人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
发明人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
IPC分类号： H01L23/34 , H01L21/00
CPC分类号： H01L23/585 , H01L23/13 , H01L23/49833 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/72 , H01L24/73 , H01L24/85 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/13025 , H01L2224/18 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/484 , H01L2224/49 , H01L2224/73257 , H01L2224/85 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/3512 , H01L2224/78 , H01L2224/29099 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.
摘要翻译：一种用于三维半导体芯片堆叠的芯片间插槽互连，特别是具有在半导体芯片上形成边缘连接的能力，其中半导体芯片安装在能够配备嵌入式电路的一个或多个芯片载体中。此外，提供了用于在半导体芯片上制造边缘连接的独特方法，用于形成半导体芯片载体，以及用于制造新颖的半导体和组合芯片载体结构。

83. 发明授权

US07462509B2 Dual-sided chip attached modules 有权
标题翻译：双面芯片连接模块
公开(公告)号：US07462509B2
公开(公告)日：2008-12-09
申请号：US11383595
申请日：2006-05-16
申请人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L24/10 , H01L23/13 , H01L23/481 , H01L23/49833 , H01L23/5385 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L2224/13 , H01L2224/13099 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H05K1/145 , H05K3/222 , H05K2201/10674 , Y10T436/171538 , Y10T436/172307 , H01L2924/00014 , H01L2924/00
摘要： An method of packaging an electronic device. The method for packaging the device including: providing a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.
摘要翻译：一种封装电子设备的方法。用于封装器件的方法包括：提供第一衬底，第二衬底和具有第一侧和相对第二侧的集成电路芯片，第一组芯片焊盘和第二组芯片焊盘，集成电路芯片的第二侧，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的相应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。

84. 发明申请

US20080213948A1 DUAL WIRED INTEGRATED CIRCUIT CHIPS 有权
标题翻译：双线集成电路板
公开(公告)号：US20080213948A1
公开(公告)日：2008-09-04
申请号：US12029575
申请日：2008-02-12
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Anthony Kendall Stamper
IPC分类号： H01L21/84
CPC分类号： H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/522 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
摘要翻译：具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二接触器件通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

85. 发明授权

US07397718B2 Determining relative amount of usage of data retaining device based on potential of charge storing device 有权
标题翻译：基于电荷存储装置的潜力确定数据保存装置的相对使用量
公开(公告)号：US07397718B2
公开(公告)日：2008-07-08
申请号：US11279639
申请日：2006-04-13
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G11C7/00
CPC分类号： G06F12/121 , G06F12/122
摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.
摘要翻译：公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

86. 发明申请

US20070267698A1 DUAL WIRED INTEGRATED CIRCUIT CHIPS 有权
标题翻译：双线集成电路板
公开(公告)号：US20070267698A1
公开(公告)日：2007-11-22
申请号：US11774853
申请日：2007-07-09
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Paul Kartschoke , Anthony Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Paul Kartschoke , Anthony Stamper
IPC分类号： H01L27/088 , H01L21/84
CPC分类号： H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/522 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
摘要翻译：具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二接触器件通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

87. 发明授权

US07298161B2 Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability 失效
标题翻译：电路和方法建立栅介质测试点可靠性与产品门可靠性之间的相关性
公开(公告)号：US07298161B2
公开(公告)日：2007-11-20
申请号：US11088953
申请日：2005-03-24
申请人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
发明人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
IPC分类号： G01R31/26
CPC分类号： G01R31/2855
摘要： A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.
摘要翻译：一种用于预测门可靠性的方法和系统。该方法包括以下步骤：施加栅极电介质测试点以获得栅极介电测试点数据，并使用测试点数据来预测栅极的可靠性。优选地，测试结构和产品结构以这样的方式集成，使得测试位置占据产品区域中的一些，并且产品本身占据产品区域的其余部分。更具体地说，优选的方法如下：（1）并联应力模式和环形振荡器或“产品”模式下的测试结构; （2）根据平行应力模式分析每个区域的现有技术状况; （3）使用面积缩放结合上述分解分布，以提高累积分布函数的威布尔斜率的置信范围; （4）在产品模式下测试环形振荡器，以确定应力失效的数量是否也是由操作退化定义的产品故障; （5）细分失败，确定第一个失败与第二个失败之间的关系，第n个失败; （6）调查哪些压力失败，如果不是第一次压力失败，更有可能导致产品按作业退化所定义的失效; 和（7）基于步骤5中的细分和步骤6中的结果，基于最可能导致失败的失败进行投影。如上所述的方法在介电应力失效和产物退化两者之间，在每个应力失效导致产物降解的情况下，以及在任何产物降解发生之前发生多于一个应力失效的情况下。这种关系可以量化。

88. 发明授权

US07285477B1 Dual wired integrated circuit chips 有权
标题翻译：双重有线集成电路芯片
公开(公告)号：US07285477B1
公开(公告)日：2007-10-23
申请号：US11383563
申请日：2006-05-16
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Anthony Kendall Stamper
IPC分类号： H01L21/30
CPC分类号： H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/522 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
摘要翻译：具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二接触器件通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

89. 发明授权

US07183142B2 FinFETs with long gate length at high density 失效
标题翻译： FinFET长栅长度为高密度
公开(公告)号：US07183142B2
公开(公告)日：2007-02-27
申请号：US10905615
申请日：2005-01-13
申请人： Brent A. Anderson , Kerry Bernstein , Edward J. Nowak
发明人： Brent A. Anderson , Kerry Bernstein , Edward J. Nowak
IPC分类号： H01L21/335
CPC分类号： H01L29/785 , H01L27/1211 , H01L29/42384 , H01L29/66795
摘要： A method of manufacturing fin-type field effect transistors (FinFETs) forms a silicon layer above a substrate, forms a mask pattern above the silicon layer using a multi-step mask formation process, patterns the silicon layer into silicon fins using the mask pattern such that the silicon fins only remain below the mask pattern, removes the mask pattern to leave the fins on the substrate, and forms gate conductors over the fins at a non-perpendicular angle to the fins.
摘要翻译：制造鳍型场效应晶体管（FinFET）的方法在衬底上形成硅层，使用多步骤掩模形成工艺在硅层上形成掩模图案，使用掩模图案将硅层图案化为硅散热片硅片仅保留在掩模图案之下，去除掩模图案以将散热片留在基板上，并且以与散热片非垂直的角度在翅片上形成栅极导体。

90. 发明申请

US20060231893A1 Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement 有权
公开(公告)号：US20060231893A1
公开(公告)日：2006-10-19
申请号：US11107611
申请日：2005-04-15
申请人： Kerry Bernstein , Jeffrey Sleight , Min Yang
发明人： Kerry Bernstein , Jeffrey Sleight , Min Yang
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L27/0922 , H01L27/1207
摘要： The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

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