专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20060232341A1 Radio frequency power amplifier 有权
标题翻译：射频功率放大器
公开(公告)号：US20060232341A1
公开(公告)日：2006-10-19
申请号：US11404802
申请日：2006-04-17
申请人： Motoyoshi Iwata , Hiroyasu Takehara , Hiroyuki Yamauchi
发明人： Motoyoshi Iwata , Hiroyasu Takehara , Hiroyuki Yamauchi
IPC分类号： H03F3/04
CPC分类号： H03F3/04 , H03F1/0261 , H03F1/302 , H03F3/189 , H03F2200/387
摘要： There are provided an RF power amplifier transistor (2), a bias supply circuit (51) which supplies a bias current to the base of the RF power amplifier transistor and a bias control circuit (52) connected between the base of the RF power amplifier transistor and bias supply circuit, and the bias control circuit is connected to the power supply (32) of the RF power amplifier transistor, thus realizing high efficiency of the RF power amplifier when the power level is low and improving the temperature characteristic of the power amplifier when the power level is low.
摘要翻译：提供了RF功率放大器晶体管（2），向RF功率放大器晶体管的基极提供偏置电流的偏置电源电路（51）和连接在RF功率放大器的基极之间的偏置控制电路（52）晶体管和偏置电源电路，并且偏置控制电路连接到RF功率放大器晶体管的电源（32），从而在功率电平低时实现RF功率放大器的高效率并且提高功率的温度特性功率电平低时的放大器。

82. 发明申请

US20050221561A1 Semiconductor integrated circuit device and method for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20050221561A1
公开(公告)日：2005-10-06
申请号：US11085579
申请日：2005-03-22
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C17/08 , G11C11/41 , G11C17/12 , H01L21/336 , H01L21/8244 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/11 , H01L27/112
CPC分类号： H01L27/105 , G11C17/12
摘要： A semiconductor integrated circuit device includes a semiconductor substrate and a ROM region, an SRAM region and a peripheral circuit region which are formed on the semiconductor substrate. Further, a column switch region is provided adjacent to the ROM region. MOS transistors in the ROM region and channel regions of access transistors in the SRAM region have substantially the same p-type impurity concentration. Accordingly, the threshold voltages of the transistors are adjusted by making use of the great dependence of the threshold voltage of the transistor on the channel width.
摘要翻译：半导体集成电路器件包括形成在半导体衬底上的半导体衬底和ROM区域，SRAM区域和外围电路区域。此外，在ROM区域附近设置列开关区域。 ROM区域中的MOS晶体管和SRAM区域中的存取晶体管的沟道区域具有基本上相同的p型杂质浓度。因此，通过利用晶体管的阈值电压对通道宽度的很大依赖性来调节晶体管的阈值电压。

83. 发明授权

US06888444B1 SIGNAL TRANSMITTING CIRCUIT, SIGNAL RECEIVING CIRCUIT, SIGNAL TRANSMITTING/RECEIVING CIRCUIT, SIGNAL TRANSMITTING METHOD, SIGNAL RECEIVING METHOD, SIGNAL TRANSMITTING/RECEIVING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT, AND CONTROL METHOD THEREOF 失效
标题翻译：信号发送电路，信号接收电路，信号发送/接收电路，信号发送方法，信号接收方法，信号发送/接收方法，半导体集成电路及其控制方法
公开(公告)号：US06888444B1
公开(公告)日：2005-05-03
申请号：US09234112
申请日：1999-01-19
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： H04L25/02 , G08B5/00
CPC分类号： H04L25/0272 , H04L25/028 , H04L25/0292
摘要： In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors. Accordingly, the signal receiving circuit composed of the inverting circuit operates statically in response to the first and second pairs of differential signals.
摘要翻译：在基于电源电位发送具有极小振幅电压的第一对差分时钟信号UCLK，基于电源电位具有极小振幅电压的第二对差分时钟信号LCLK，LXCLK时，作为信号接收电路的反相电路由CMOS反相电路构成。构成CMOS反相电路的PMOS晶体管具有接收第一对差分时钟信号的栅电极和源电极。构成CMOS反相电路的NMOS晶体管具有接收第二对差分时钟信号的栅电极和源电极。当差分时钟信号的电位发生变化时，两个晶体管的各个栅极和源极之间的电位在相反的方向上移动，这确实切断晶体管。因此，由反相电路构成的信号接收电路根据第一和第二对差分信号静态工作。

84. 发明授权

US06871338B2 Semiconductor integrated circuit device and method for designing the same 失效
标题翻译：半导体集成电路器件及其设计方法
公开(公告)号：US06871338B2
公开(公告)日：2005-03-22
申请号：US10281300
申请日：2002-10-28
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G06F17/50 , H01L21/82 , H01L21/8244 , H01L27/10 , H01L27/11
CPC分类号： G06F17/5068 , G03F1/36
摘要： A method for designing a semiconductor integrated circuit device, the method has the steps of producing, for a plurality of placement regions on each of which a design pattern is to be placed, first layout data having a first expected value based on a first layout design rule, producing, if a difference between the first expected data and an expected finished size after fabrication of the first layout data falls within an error tolerance for a standard value, first OPC data by correcting the first layout data, producing, if the plurality of placement regions include an out-of-tolerance region for which the first OPC data falling within the error tolerance cannot be produced, second layout data having a second expected value for the out-of-tolerance region based on a second layout design rule, producing second OPC data by correcting the second layout data such that an expected finished size after fabrication of the second layout data falls within the error tolerance for the standard value, and producing mask data by using the first OPC data and the second OPC data.
摘要翻译：一种用于设计半导体集成电路器件的方法，所述方法具有以下步骤：对于要放置设计图案的多个放置区域，产生基于第一布局设计具有第一预期值的第一布局数据规则，如果第一布局数据的制造之后的第一预期数据和预期成品尺寸之间的差异落在对于标准值的误差容差内，则通过校正第一布局数据来产生第一OPC数据，如果多个放置区域包括不能产生落在误差公差内的第一OPC数据的第二布局数据，其中第二布局数据具有基于第二布局设计规则的超出公差区域的第二预期值，产生通过校正第二布局数据使得第二布局数据的制造之后的预期成品尺寸落在标准值的误差容差内的第二OPC数据 ue，并通过使用第一OPC数据和第二OPC数据产生掩模数据。

85. 发明授权

US06806102B2 Method of fabricating semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US06806102B2
公开(公告)日：2004-10-19
申请号：US10288470
申请日：2002-11-06
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： H01L2166
CPC分类号： H01L22/20 , H01L21/28017 , H01L21/76819 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor integrated circuit device of the present invention forms an insulating film on a semiconductor wafer and forms a mask pattern containing a functional element or a wire on the formed insulating film. Dimensions of the mask pattern are changed in accordance with an amount of process variation occurring in the thickness or dielectric constant of the insulating film during the formation of the insulating film.
摘要翻译：本发明的半导体集成电路器件的制造方法在半导体晶片上形成绝缘膜，并在形成的绝缘膜上形成包含功能元件或线的掩模图案。根据在形成绝缘膜期间绝缘膜的厚度或介电常数发生的工艺变化量，改变掩模图案的尺寸。

86. 发明授权

US06711044B2 Semiconductor memory device with a countermeasure to a signal delay 失效
标题翻译：半导体存储器件具有信号延迟的对策
公开(公告)号：US06711044B2
公开(公告)日：2004-03-23
申请号：US10171790
申请日：2002-06-17
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C506
CPC分类号： G11C5/063 , G11C7/18 , H01L27/1104
摘要： A semiconductor memory device of the present invention includes: a substrate; a plurality of memory cells arranged in a matrix pattern on a primary surface of the substrate; a sense amplifier provided in each column for detecting data of the memory cells that are arranged along the column; a plurality of wiring layers formed on the substrate; and a plurality of data lines provided in each column and connected to the memory cells that are arranged in the column, wherein the data lines are connected commonly to the sense amplifier but via different paths, and a data line having a longer path length is provided by using a wiring layer that is on a higher level.
摘要翻译：本发明的半导体存储器件包括：衬底; 在基板的主表面上以矩阵图案布置的多个存储单元; 每个列中提供的用于检测沿着列布置的存储器单元的数据的读出放大器; 形成在所述基板上的多个布线层; 以及设置在各列中并连接到列中的存储单元的多条数据线，其中数据线共同连接到读出放大器但经由不同的路径，并且提供了具有较长路径长度的数据线通过使用更高级别的布线层。

87. 发明授权

US06597612B2 Sense amplifier circuit 有权
标题翻译：感应放大电路
公开(公告)号：US06597612B2
公开(公告)日：2003-07-22
申请号：US10173155
申请日：2002-06-18
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C700
CPC分类号： G11C7/065
摘要： To prevent a resistive delay in a bitline disconnecting circuit, an NMOS latch composing a part of a CMOS latch is composed of four series NMOS transistors, two of which have respective gate electrodes cross-coupled directly to a pair of bitlines without the interposition of the bitline disconnecting circuit therebetween and the other two of which have respective gate electrodes cross-coupled to a pair of first-stage output nodes in a stage subsequent to the bitline disconnecting circuit.
摘要翻译：为了防止位线断开电路中的电阻性延迟，组成CMOS锁存器的一部分的NMOS锁存器由四个串联NMOS晶体管组成，其中两个NMOS晶体管具有相应的栅极电极直接交叉耦合到一对位线，而不插入位线断开电路之间，其他两个具有在位线断开电路之后的阶段中交叉耦合到一对第一级输出节点的相应栅电极。

88. 发明授权

US06339355B1 Offsetting comparator device and comparator circuit 失效
标题翻译：偏移比较器器件和比较器电路
公开(公告)号：US06339355B1
公开(公告)日：2002-01-15
申请号：US09461381
申请日：1999-12-15
申请人： Hiroyuki Yamauchi , Yutaka Terada
发明人： Hiroyuki Yamauchi , Yutaka Terada
IPC分类号： H03L500
CPC分类号： H03F3/45717
摘要： An offsetting comparator device includes master and slave comparator circuits and a reference differential voltage generator. The master comparator circuit supplies a sensed current corresponding to a potential difference represented by a differential signal on a transmission line. The reference differential voltage generator generates a reference differential voltage based on an intermediate potential of the differential signal. And the slave comparator circuit supplies a current corresponding to the potential difference as offset current. The offsetting comparator device outputs a differential current between the sensed and offset currents and therefore shows an offset in its input/output characteristics. The master and slave comparator circuits have the same circuit configuration. Thus, if the characteristic of the sensed current output from the master comparator circuit has changed due to a potential level variation of the differential signal, then the characteristic of the offset current also changes similarly. Thus, the offsetting comparator device can obtain a constant offset voltage even if the potential level of the differential signal has changed.
摘要翻译：偏置比较器装置包括主比较器电路和参考差分电压发生器。主比较器电路在传输线上提供与由差分信号表示的电位差相对应的感测电流。参考差分电压发生器基于差分信号的中间电位产生参考差分电压。并且从比较器电路提供对应于电位差的电流作为偏移电流。偏移比较器装置在感测和偏移电流之间输出差分电流，因此在其输入/输出特性中显示偏移。主从比较器电路具有相同的电路配置。因此，如果从主比较器电路输出的检测电流的特性由于差分信号的电位电平变化而改变，则偏移电流的特性也发生类似变化。因此，即使差分信号的电位电平已经改变，偏移比较器装置也可获得恒定的偏移电压。

89. 发明授权

US06297675B1 Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses 有权
标题翻译：具有串行可互连数据总线的半导体集成电路和半导体集成电路系统
公开(公告)号：US06297675B1
公开(公告)日：2001-10-02
申请号：US09478530
申请日：2000-01-06
申请人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
发明人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
IPC分类号： H03B100
CPC分类号： H03K19/018514 , Y10T307/549
摘要： A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved. In this manner, the present invention is applicable to reduction of current dissipation when data should be transmitted at high speeds through multiple data bus pairs that are driven with a current supplied.
摘要翻译：在第一和第二芯片之间提供数据线对和选通线对，以在它们之间交换数据。第一芯片包括输出电路和用于控制输出电路的控制器。第二芯片包括输入电路。例如，输出电路将电流从电源提供给数据线之一。然后，输入电路通过一对端子电阻和另一条数据线将接收的电流反馈到输出电路。随后，输出电路将反馈的直流电流提供给选通线之一。作为响应，输入电路通过另一对端子电阻器和另一个选通线路将接收到的电流再次反馈到输出电路。然后将反馈电流排到地面。因此，与以相同的电流量驱动数据和选通线对相比，电流消耗可以减半。以这种方式，本发明可应用于当通过以所提供的电流驱动的多个数据总线对以高速传输数据时，减少电流消耗。

90. 发明授权

US06055276A Signal transmitting circuit and method with selection among differential pairs 失效
标题翻译：信号传输电路和差分对选择方法
公开(公告)号：US06055276A
公开(公告)日：2000-04-25
申请号：US538858
申请日：1995-10-04
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： H04B3/02 , H04L25/08
CPC分类号： H04B3/02 , H04L25/08
摘要： In the early half of one period of a main clock, one multiplexer selects a signal Ain, while the other multiplexer selects an inverted signal /Ain. Consequently, the signal Ain is transmitted to a signal line assigned to the signal line Ain, while the signal /Ain is transmitted to a signal line assigned to a signal Bin, thereby accomplishing differential transmission of the signal Ain. In the late half of one period of the main clock, the above one multiplexer selects an inverted signal /Bin, while the above other multiplexer selects the signal Bin. Consequently, the inverted signal /Bin is transmitted to the signal line assigned to the signal Ain, while the signal Bin is transmitted to the signal line assigned to the signal Bin, thereby accomplishing differential transmission of the signal Bin. Since differential transmission is thus accomplished with no increase in the number of wires, power saving can be achieved by data transfer with a small amplitude.
摘要翻译：在主时钟的一个周期的早半时期，一个多路复用器选择信号Ain，而另一个多路复用器选择反相信号/ Ain。因此，信号Ain被发送到分配给信号线Ain的信号线，而信号Ain被发送到分配给信号Bin的信号线，从而实现信号Ain的差分传输。在主时钟的一个周期的后半段中，上述一个多路复用器选择反相信号/ Bin，而上述另一个多路复用器选择信号Bin。因此，将反相信号/ Bin发送到分配给信号Ain的信号线，同时信号Bin被发送到分配给信号Bin的信号线，从而实现信号Bin的差分传输。由于差分传输是通过不增加导线来实现的，因此可以通过小振幅的数据传输实现功率节省。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式