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81. 发明申请

US20120280290A1 LOCAL INTERCONNECT STRUCTURE SELF-ALIGNED TO GATE STRUCTURE 有权
标题翻译：局部互连结构自对准结构
公开(公告)号：US20120280290A1
公开(公告)日：2012-11-08
申请号：US13102073
申请日：2011-05-06
申请人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
发明人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L27/0207 , H01L21/28518 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/1104 , H01L29/41783 , H01L29/66545 , H01L29/6659 , H01L29/7834
摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.
摘要翻译：采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。

82. 发明申请

US20120261792A1 SOI DEVICE WITH DTI AND STI 有权
标题翻译：具有DTI和STI的SOI器件
公开(公告)号：US20120261792A1
公开(公告)日：2012-10-18
申请号：US13088376
申请日：2011-04-17
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/12 , H01L21/76
CPC分类号： H01L21/76229 , H01L21/743 , H01L21/76232 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： An SOI structure including a semiconductor on insulator (SOI) substrate including a top silicon layer, an intermediate buried oxide (BOX) layer and a bottom substrate; at least two wells in the bottom substrate; a deep trench isolation (DTI) separating the two wells, the DTI having a top portion extending through the BOX layer and top silicon layer and a bottom portion within the bottom substrate wherein the bottom portion has a width that is larger than a width of the top portion; and at least two semiconductor devices in the silicon layer located over one of the wells, the at least two semiconductor devices being separated by a shallow trench isolation within the top silicon layer.
摘要翻译：包括绝缘体上半导体（SOI）衬底的SOI结构，包括顶部硅层，中间掩埋氧化物（BOX）层和底部衬底; 底部底物中至少有两口井; 分离两个阱的深沟槽隔离（DTI），DTI具有延伸穿过BOX层和顶部硅层的顶部和底部衬底内的底部部分，其中底部部分的宽度大于顶部以及位于所述阱之一上的所述硅层中的至少两个半导体器件，所述至少两个半导体器件由所述顶部硅层内的浅沟槽隔离隔开。

83. 发明申请

US20120074494A1 STRAINED THIN BODY SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND DEVICE 有权
标题翻译：应变薄体半导体绝缘体基板和器件
公开(公告)号：US20120074494A1
公开(公告)日：2012-03-29
申请号：US13301360
申请日：2011-11-21
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/786
CPC分类号： H01L21/84 , H01L21/76283 , H01L29/66772 , H01L29/7842 , H01L29/7847 , H01L29/78603
摘要： A method of forming a strained, semiconductor-on-insulator substrate includes forming a second semiconductor layer on a first semiconductor substrate. The second semiconductor is lattice matched to the first semiconductor substrate such that the second semiconductor layer is subjected to a first directional stress. An active device semiconductor layer is formed over the second semiconductor layer such that the active device semiconductor layer is initially in a relaxed state. One or more trench isolation structures are formed through the active device layer and through the second semiconductor layer so as to relax the second semiconductor layer below the active device layer and impart a second directional stress on the active device layer opposite the first directional stress.
摘要翻译：形成应变绝缘体上半导体衬底的方法包括在第一半导体衬底上形成第二半导体层。第二半导体与第一半导体衬底晶格匹配，使得第二半导体层经受第一定向应力。在第二半导体层上形成有源器件半导体层，使得有源器件半导体层初始处于松弛状态。通过有源器件层和通过第二半导体层形成一个或多个沟槽隔离结构，以便使有源器件层下方的第二半导体层松弛，并在与第一方向应力相反的有源器件层上施加第二方向应力。

84. 发明申请

US20120025288A1 SOI Trench DRAM Structure With Backside Strap 有权
标题翻译： SOI沟槽DRAM结构带背面带
公开(公告)号：US20120025288A1
公开(公告)日：2012-02-02
申请号：US12847208
申请日：2010-07-30
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/8242 , H01L27/108 , H01L21/02
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a silicon-on-insulator substrate having of a top silicon layer overlying an insulation layer, where the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, where at least a first portion of the backside strap underlies the doped portion of the top silicon layer, where the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, where the second epitaxially-deposited material further at least partially overlies the first portion of the backside strap.
摘要翻译：在一个示例性实施例中，一种半导体结构，包括：绝缘体上硅衬底，其具有覆盖绝缘层的顶部硅层，其中所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，其中背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，其中背面带在顶部硅层的第一端处耦合到顶部硅层的掺杂部分背面带和在背面带的第二端处的电容器; 以及第二外延沉积材料，其至少部分地覆盖在顶部硅层的掺杂部分上，其中第二外延沉积材料进一步至少部分地覆盖在背面带的第一部分上。

85. 发明申请

US20110291202A1 DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE 有权
标题翻译：减少接头泄漏的装置和方法
公开(公告)号：US20110291202A1
公开(公告)日：2011-12-01
申请号：US12789839
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66628 , H01L21/26513 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834
摘要： A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.
摘要翻译：用于减少半导体结中的结漏电的器件和方法包括在器件的源极/漏极区域中形成刻面的凸起结构。掺杂剂从小面凸起结构扩散到小平面凸起结构下面的基底中以形成源极/漏极区域。在刻面凸起结构上施加喷洒注入，以在源/漏区的衬底中产生多深度掺杂物分布。

86. 发明授权

US08642415B2 Semiconductor substrate with transistors having different threshold voltages 失效
标题翻译：具有不同阈值电压的晶体管的半导体衬底
公开(公告)号：US08642415B2
公开(公告)日：2014-02-04
申请号：US13487511
申请日：2012-06-04
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Pranita Kulkarni , Alexander Reznicek
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.
摘要翻译：公开了一种制造半导体集成电路的方法。该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

87. 发明授权

US08710588B2 Implant free extremely thin semiconductor devices 有权
标题翻译：植入物非常薄的半导体器件
公开(公告)号：US08710588B2
公开(公告)日：2014-04-29
申请号：US13595025
申请日：2012-08-27
申请人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78621 , H01L29/78654
摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.
摘要翻译：公开了半导体器件和制造半导体器件的方法。在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。以这种方式，半导体层成为非常薄的绝缘体上半导体层。在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。

88. 发明申请

US20130056802A1 IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES 有权
标题翻译：嵌入式无限超薄半导体器件
公开(公告)号：US20130056802A1
公开(公告)日：2013-03-07
申请号：US13595025
申请日：2012-08-27
申请人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
IPC分类号： H01L29/78
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78621 , H01L29/78654
摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.
摘要翻译：公开了半导体器件和制造半导体器件的方法。在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。以这种方式，半导体层成为非常薄的绝缘体上半导体层。在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。

89. 发明申请

US20110115022A1 IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES 有权
标题翻译：嵌入式无限超薄半导体器件
公开(公告)号：US20110115022A1
公开(公告)日：2011-05-19
申请号：US12621299
申请日：2009-11-18
申请人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78621 , H01L29/78654
摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer. Epitaxially growing the extremely thin semiconductor layer on the Ge layer ensures good thickness control across the wafer. This process could be used for SOI or bulk wafers.
摘要翻译：公开了半导体器件和制造半导体器件的方法。在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。以这种方式，半导体层成为非常薄的绝缘体上半导体层。在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。在Ge层上外延生长极薄的半导体层确保跨晶片的良好的厚度控制。该工艺可用于SOI或体晶片。

90. 发明授权

US08673699B2 Semiconductor structure having NFET extension last implants 有权
标题翻译：具有NFET延伸最后植入物的半导体结构
公开(公告)号：US08673699B2
公开(公告)日：2014-03-18
申请号：US13551054
申请日：2012-07-17
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Amlan Majumdar , Stefan Schmitz
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Amlan Majumdar , Stefan Schmitz
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
摘要翻译：一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，邻近 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。在PFET部分的RSD上形成非晶硅层。在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

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