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81. 发明授权

US08995186B2 Memory cells, memory cell arrays, methods of using and methods of making 有权
标题翻译：存储单元，存储单元阵列，使用方法和制作方法
公开(公告)号：US08995186B2
公开(公告)日：2015-03-31
申请号：US14148373
申请日：2014-01-06
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： G11C14/00 , H01L45/00 , G11C11/404 , H01L27/24 , H01L29/66 , H01L29/78 , H01L29/788 , H01L27/105 , G11C11/56 , G11C16/04
CPC分类号： G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0097 , G11C14/0018 , G11C14/0045 , G11C16/0416 , G11C2211/4016 , G11C2213/76 , G11C2213/79 , H01L27/1023 , H01L27/1052 , H01L27/10802 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/7881 , H01L45/06 , H01L45/144 , H01L45/145
摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.
摘要翻译：提供半导体存储单元和存储单元阵列在至少一个实施例中，存储单元包括具有顶表面的衬底，该衬底具有选自p型导电类型和n型导电类型的第一导电类型 ; 具有选自p型和n型导电类型的第二导电类型的第一区域，所述第二导电类型不同于所述第一导电类型，所述第一区域形成在所述基板中并暴露在所述顶表面处; 具有第二导电类型的第二区域，第二区域形成在基板中，与第一区域间隔开并暴露在顶表面处; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 形成在所述第一和第二区域与所述掩埋层之间的体区，所述体区具有第一导电类型; 位于第一和第二区域之间并位于顶部表面之上的门; 以及非易失性存储器，被配置为在从身体区域传送时存储数据。

82. 发明申请

US20140159156A1 Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making 有权
标题翻译：具有减少触点数量的紧凑型半导体存储器件，操作方法和制造方法
公开(公告)号：US20140159156A1
公开(公告)日：2014-06-12
申请号：US14177819
申请日：2014-02-11
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： H01L27/108
CPC分类号： H01L27/10802 , G11C11/34 , G11C11/404 , G11C11/409 , G11C14/0018 , G11C16/0416 , G11C2211/4016 , H01L27/108 , H01L27/10826 , H01L27/115 , H01L27/11521 , H01L27/1203 , H01L27/1211 , H01L29/16 , H01L29/7841 , H01L29/7881
摘要： An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
摘要翻译：一种包括半导体存储单元的链路或串的集成电路，其中每个存储单元包括用于存储数据的浮动体区域。链路或串包括至少一个被配置为将存储器单元电连接到至少一个控制线的触点，并且串或链接中的触点的数量与串或链接中的存储器单元的数量相同或小于。

83. 发明申请

US20140117299A1 Memory Cells, Memory Cell Arrays, Methods of Using and Methods of Making 有权
标题翻译：记忆单元，记忆单元阵列，使用方法和制作方法
公开(公告)号：US20140117299A1
公开(公告)日：2014-05-01
申请号：US14148373
申请日：2014-01-06
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： H01L45/00
CPC分类号： G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0097 , G11C14/0018 , G11C14/0045 , G11C16/0416 , G11C2211/4016 , G11C2213/76 , G11C2213/79 , H01L27/1023 , H01L27/1052 , H01L27/10802 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/7881 , H01L45/06 , H01L45/144 , H01L45/145
摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.
摘要翻译：提供半导体存储单元和存储单元阵列在至少一个实施例中，存储单元包括具有顶表面的衬底，该衬底具有选自p型导电类型和n型导电类型的第一导电类型 ; 具有选自p型和n型导电类型的第二导电类型的第一区域，所述第二导电类型不同于所述第一导电类型，所述第一区域形成在所述基板中并暴露在所述顶表面处; 具有第二导电类型的第二区域，第二区域形成在基板中，与第一区域间隔开并暴露在顶表面处; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 形成在所述第一和第二区域与所述掩埋层之间的体区，所述体区具有第一导电类型; 位于第一和第二区域之间并位于顶部表面之上的门; 以及非易失性存储器，被配置为在从身体区域传送时存储数据。

84. 发明授权

US08582359B2 Dual-port semiconductor memory and first-in first-out (FIFO) memory having electrically floating body transistor 有权
标题翻译：双端口半导体存储器和先进先出（FIFO）存储器，具有电浮体晶体管
公开(公告)号：US08582359B2
公开(公告)日：2013-11-12
申请号：US13296402
申请日：2011-11-15
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： G11C11/34
CPC分类号： H01L27/10802 , G11C7/00 , G11C8/10 , G11C8/16 , G11C11/40 , G11C11/403 , G11C11/405 , H01L27/1023 , H01L27/105 , H01Q1/2283
摘要： Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
摘要翻译：多端口半导体存储器单元包括配置为被充电到指示存储器单元的存储器状态的电平的公共浮动体区域。多端口半导体存储单元包括与所述浮体区域相接合的多个栅极和导电区域。公开了用于制造存储器件的存储器单元阵列和操作所述存储器阵列的方法。

85. 发明授权

US08559257B2 Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle 有权
标题翻译：使用可控硅整流器原理操作具有浮体晶体管的半导体存储器件的方法
公开(公告)号：US08559257B2
公开(公告)日：2013-10-15
申请号：US13244916
申请日：2011-09-26
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： G11C7/00
CPC分类号： H01L27/10802 , G11C11/404 , G11C11/406 , G11C11/4076 , G11C11/4096 , G11C2211/4016 , H01L29/7841
摘要： A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region.
摘要翻译：提供一种保持半导体动态随机存取存储单元的数据状态的方法，其中存储单元包括由具有选自p型导电型和n型导电型的第一导电类型的材料制成的衬底; 具有选自p型和n型导电类型的第二导电类型的第一区域，所述第二导电类型不同于所述第一导电类型; 具有第二导电类型的第二区域，第二区域与第一区域间隔开; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 具有第一导电类型的体区; 以及位于第一和第二区域之间并且邻近身体区域的门。

86. 发明授权

US08472249B2 Semiconductor memory having both volatile and non-volatile functionality and method of operating 有权
公开(公告)号：US08472249B2
公开(公告)日：2013-06-25
申请号：US13246582
申请日：2011-09-27
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C14/0018 , G11C11/404 , G11C16/0408 , G11C16/0466 , G11C16/0483 , G11C16/225 , G11C2211/4016 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L27/10897 , H01L27/11521 , H01L27/11526 , H01L27/11531 , H01L27/11568 , H01L27/11573 , H01L27/1203 , H01L29/0649 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/785 , H01L29/7885 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

87. 发明申请

US20130148422A1 Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating 有权
标题翻译：具有挥发性和非挥发性功能的半导体存储器和操作方法
公开(公告)号：US20130148422A1
公开(公告)日：2013-06-13
申请号：US13758646
申请日：2013-02-04
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： H01L29/78 , G11C11/40
CPC分类号： H01L27/10802 , G11C11/40 , G11C11/404 , G11C14/0018 , G11C16/0416 , G11C2211/4016 , H01L29/66825 , H01L29/66833 , H01L29/78 , H01L29/7841 , H01L29/7881
摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.
摘要翻译：具有易失性和非易失性模式和操作方法的半导体存储器。半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在基板的第二位置处嵌入基板并具有第二导电类型，使得具有第一导电类型的基板的至少一部分位于第一和第二位置之间，并且用作浮体以存储易失性存储器中的数据; 位于所述第一和第二位置之间且位于所述基板的表面之上并且通过绝缘层与所述表面绝缘的浮栅或捕获层; 浮动栅极或俘获层被配置为在中断对存储器单元的电力时，接收由易失性存储器存储的数据的传输并将数据作为非易失性存储器存储在浮动栅极或俘获层中; 以及位于浮置栅极或俘获层上方的控制栅极和位于浮置栅极或捕获层与控制栅极之间的第二绝缘层。

88. 发明申请

US20130094280A1 Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Comprising Resistive Change Material and Method of Operating 有权
公开(公告)号：US20130094280A1
公开(公告)日：2013-04-18
申请号：US13652457
申请日：2012-10-15
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： H01L45/00 , G11C11/21 , H01L29/82
CPC分类号： G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

89. 发明授权

US08294193B2 Semiconductor memory having both volatile and non-volatile functionality and method of operating 有权
标题翻译：具有易失性和非易失性功能以及操作方法的半导体存储器
公开(公告)号：US08294193B2
公开(公告)日：2012-10-23
申请号：US12915831
申请日：2010-10-29
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： H01L29/788
CPC分类号： G11C14/0018 , G11C11/404 , G11C16/0408 , G11C16/0466 , G11C16/0483 , G11C16/225 , G11C2211/4016 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L27/10897 , H01L27/11521 , H01L27/11526 , H01L27/11531 , H01L27/11568 , H01L27/11573 , H01L27/1203 , H01L29/0649 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/785 , H01L29/7885 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory, first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer.
摘要翻译：具有易失性和非易失性模式和操作方法的半导体存储器。半导体存储单元包括从衬底延伸的翅片结构，鳍结构包括具有第一导电类型的浮动衬底区域，配置为将数据存储为易失性存储器，与浮置衬底区域接口的第一和第二区域，第一和第具有第二导电类型的第二区域; 位于浮置衬底区域的相对侧的第一和第二浮栅或俘获层; 位于所述浮置衬底区域和所述浮置栅极或俘获层之间的第一绝缘层，所述浮置栅极或俘获层被配置为接收由所述易失性存储器存储的数据的传送，并将所述数据作为非易失性存储器存储在所述浮置栅极或俘获层中在中断存储器单元的电源时; 围绕浮动栅极或捕获层和浮置衬底区域的控制栅极; 以及位于所述浮置栅极或俘获层之间的第二绝缘层和所述控制栅极; 所述衬底包括将所述浮置衬底区域与所述隔离层下方的所述衬底的一部分隔离的隔离层。

90. 发明授权

US08194451B2 Memory cells, memory cell arrays, methods of using and methods of making 有权
标题翻译：存储单元，存储单元阵列，使用方法和制作方法
公开(公告)号：US08194451B2
公开(公告)日：2012-06-05
申请号：US12552903
申请日：2009-09-02
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： G11C14/00
CPC分类号： G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0097 , G11C14/0018 , G11C14/0045 , G11C16/0416 , G11C2211/4016 , G11C2213/76 , G11C2213/79 , H01L27/1023 , H01L27/1052 , H01L27/10802 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/7881 , H01L45/06 , H01L45/144 , H01L45/145
摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.
摘要翻译：提供半导体存储单元和存储单元阵列在至少一个实施例中，存储单元包括具有顶表面的衬底，该衬底具有选自p型导电类型和n型导电类型的第一导电类型 ; 具有选自p型和n型导电类型的第二导电类型的第一区域，所述第二导电类型不同于所述第一导电类型，所述第一区域形成在所述基板中并暴露在所述顶表面处; 具有第二导电类型的第二区域，第二区域形成在基板中，与第一区域间隔开并暴露在顶表面处; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 形成在所述第一和第二区域与所述掩埋层之间的体区，所述体区具有第一导电类型; 位于第一和第二区域之间并位于顶部表面之上的门; 以及非易失性存储器，被配置为在从身体区域传送时存储数据。

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