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81. 发明授权

US08229989B2 Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 有权
标题翻译：用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法
公开(公告)号：US08229989B2
公开(公告)日：2012-07-24
申请号：US12238500
申请日：2008-09-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

82. 发明授权

US08166085B2 Reducing the latency of sum-addressed shifters 失效
标题翻译：减少和寻址移位器的延迟
公开(公告)号：US08166085B2
公开(公告)日：2012-04-24
申请号：US12105726
申请日：2008-04-18
申请人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F15/00 , G06F7/38
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译：本发明提供了作为多个数字的函数的移位量的计算。至少一个解码器和至少一个加法器并联耦合。移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。

83. 发明授权

US08117579B2 LSSD compatibility for GSD unified global clock buffers 有权
标题翻译： LSSD兼容GSD统一全局时钟缓冲区
公开(公告)号：US08117579B2
公开(公告)日：2012-02-14
申请号：US12023337
申请日：2008-01-31
申请人： James Douglas Warnock , Wendel Dieter , David E. Lackey , William Vincent Huott , Leon Jacob Sigal , Louis Bernard Bushard , Sang Hoo Dhong
发明人： James Douglas Warnock , Wendel Dieter , David E. Lackey , William Vincent Huott , Leon Jacob Sigal , Louis Bernard Bushard , Sang Hoo Dhong
IPC分类号： G06F17/50
CPC分类号： G01R31/318594 , G01R31/318552
摘要： A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.
摘要翻译：提供了一种方法，系统和程序，用于使用中间时钟信号和一个或多个第一模式控制信号从一般扫描设计（GSD）时钟缓冲器产生电平敏感扫描设计（LSSD）时钟信号，以产生多个LSSD时钟信号从GSD时钟缓冲器的输出部分接收中间时钟信号和第一模式控制信号，其中GSD时钟缓冲器还被配置为响应于接收到GSD模式产生多个GSD时钟信号，产生来自GSD时钟缓冲器的输入部分的中间时钟信号响应于接收GSD模式信号。

84. 发明授权

US07617338B2 Memory with combined line and word access 有权
标题翻译：内存具有组合的行和字访问
公开(公告)号：US07617338B2
公开(公告)日：2009-11-10
申请号：US11050040
申请日：2005-02-03
申请人： Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Osamu Takahashi
发明人： Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Osamu Takahashi
IPC分类号： G06F13/28 , G06F5/00
CPC分类号： G06F13/28 , G06F13/1626 , G06F13/1663
摘要： A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.
摘要翻译：提出了一种具有组合线和字访问的存储器的处理器的系统。系统执行窄读/写存储器访问，并使用多路复用器和锁存器对相同存储体进行宽读/写存储器存取以指导数据。该系统使用窄读/写存储器访问处理16字节加载/请求请求，并使用宽读/写存储器访问处理128字节的DMA和指令提取请求。在DMA请求期间，系统在一个指令周期内将16个DMA操作写入/读取存储器。通过这样做，内存可用于在十五个其他指令周期内处理加载/存储或指令提取请求。

85. 发明授权

US07490119B2 High speed adder design for a multiply-add based floating point unit 失效
标题翻译：用于基于加法的浮点单元的高速加法器设计
公开(公告)号：US07490119B2
公开(公告)日：2009-02-10
申请号：US10733839
申请日：2003-12-11
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/42 , G06F7/38
CPC分类号： G06F7/483 , G06F7/5443
摘要： An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译：提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的装置和计算机程序产品。改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。进位网络同时执行结束进位功能并且独立于优化加法器功能的其他所需功能。此外，还使用最小数量的多路复用器来减少多路复用器延迟。

86. 发明申请

US20080263336A1 Processor Having Efficient Function Estimate Instructions 审中-公开
标题翻译：具有高效功能估计指令的处理器
公开(公告)号：US20080263336A1
公开(公告)日：2008-10-23
申请号：US12145482
申请日：2008-06-24
申请人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F9/302
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译：高精度浮点函数估计分为两个指令：低精度表查找指令和线性插值指令。可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤估计。因此，与专用硬件相比，产生的开销大大降低，同时仍保持统一的FPU延迟，这允许更简单的控制逻辑。

87. 发明授权

US07392270B2 Apparatus and method for reducing the latency of sum-addressed shifters 有权
标题翻译：用于减少和寻址移位器的延迟的装置和方法
公开(公告)号：US07392270B2
公开(公告)日：2008-06-24
申请号：US10902475
申请日：2004-07-29
申请人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F7/00 , G06F7/38
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译：本发明提供了作为多个数字的函数的移位量的计算。至少一个解码器和至少一个加法器并联耦合。移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。

88. 发明授权

US07043579B2 Ring-topology based multiprocessor data access bus 失效
标题翻译：基于环形拓扑的多处理器数据访问总线
公开(公告)号：US07043579B2
公开(公告)日：2006-05-09
申请号：US10313741
申请日：2002-12-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , John Samuel Liberty , Peichun Peter Liu
发明人： Sang Hoo Dhong , Harm Peter Hofstee , John Samuel Liberty , Peichun Peter Liu
IPC分类号： G06F13/00
CPC分类号： G06F13/4243
摘要： The present invention provides a data access ring. The data access ring has a plurality of attached processor units (APUs) and a local store associated with each APU. The data access ring has a data command ring, coupled to the plurality of APUs. The data command ring is employable to carry indicia of a selection of one of the plurality of APUs to the APUs. The data access ring also has a data address ring, coupled to the plurality of APUs. The data address ring is further employable to carry indicia of a memory location to the selected APU a predetermined number of clock cycles after the data command ring carries the indicia of the selection of one of the plurality of APUs. The data access ring also has a data transfer ring, coupled to the plurality of APUs. The data transfer ring is employable to transfer data to or from the memory location associated with the APU a predetermined number of clock cycles after the data address ring carries the indicia of the memory location to the selected APU.
摘要翻译：本发明提供一种数据访问环。数据访问环具有多个附接的处理器单元（APU）和与每个APU相关联的本地存储器。数据访问环具有耦合到多个APU的数据命令环。数据命令环可用于将多个APU中的一个APU的选择的标记携带到APU。数据访问环还具有耦合到多个APU的数据地址环。数据地址环还可用于在数据命令环携带多个APU中的一个APU的选择的标记之后，将所选择的APU的存储位置的标记携带预定数量的时钟周期。数据访问环还具有耦合到多个APU的数据传送环。在数据地址环将存储器位置的标记传送到所选择的APU之后，数据传送环可用于将数据传送到与APU相关联的存储器位置的数据到预定数量的时钟周期。

89. 发明授权

US06898135B2 Latch type sense amplifier method and apparatus 失效
标题翻译：锁存型读出放大器的方法和装置
公开(公告)号：US06898135B2
公开(公告)日：2005-05-24
申请号：US10606587
申请日：2003-06-26
申请人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/06 , G11C7/10 , G11C7/00
CPC分类号： G11C7/1069 , G11C7/065 , G11C7/1051
摘要： Disclosed is an apparatus for and a method of overcoming signal delay problems in a read-out path occurring in connection with pipelined memory circuits. A latch type sense amplifier (SA) is used to receive the memory cell logic levels during a pre-charge state in a cycle prior to read-out. Thus, the SA may quickly provide an output signal during a read latch clock cycle. The SA output is passed through a dynamically enabled logic circuit to a latch circuit for holding the receiving logic value for use in the next clock cycle.
摘要翻译：公开了一种克服与流水线存储器电路相关的读出路径中的信号延迟问题的装置和方法。闩锁型读出放大器（SA）用于在读出之前的一个周期中的预充电状态期间接收存储单元逻辑电平。因此，SA可以在读取锁存时钟周期期间快速提供输出信号。 SA输出通过一个动态使能的逻辑电路被传送到一个锁存电路，用于保持接收逻辑值用于下一个时钟周期。

90. 发明授权

US06772368B2 Multiprocessor with pair-wise high reliability mode, and method therefore 失效
标题翻译：具有成对的高可靠性模式的多处理器和方法
公开(公告)号：US06772368B2
公开(公告)日：2004-08-03
申请号：US09734117
申请日：2000-12-11
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Ravi Nair , Steven Douglas Posluszny
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Ravi Nair , Steven Douglas Posluszny
IPC分类号： G06F1116
CPC分类号： G06F11/1641 , G06F9/30189 , G06F9/3861 , G06F9/3885 , G06F11/1407 , G06F2201/845
摘要： In one embodiment a multiprocessing apparatus includes a first processor and a second processor. Each of the processors have their own data and instruction caches to support independent operation. In a normal mode the processors independently execute separate instruction streams. Each of the processors has a respective signature generator. The system also includes a compare unit coupled to the signature generators. In a high reliability mode, both processors execute the same instruction stream. That is, each processor computes a version of a result for ones of the instructions in the stream. Responsive to the respective versions, the respective signature generators assert signatures to the compare unit, so that a faulting instruction may be detected. In another aspect, each processor has its own respective commit logic. The compare unit signals the commit logic in each respective processor that the possibility has been eliminated of a calculation interrupt arising for that instruction, once the compare unit receives signatures for corresponding versions of a result, but only if the signatures match. This permits the commit logic to commit the result. If the signatures do not match, the compare unit signals the commit logic that the corresponding instruction has faulted. The commit logic permits instructions prior to the faulting instruction in program order to continue execution, but initiates flushing of results that were produced by the faulting instruction and at least some instructions subsequent in program order to the faulting instruction.
摘要翻译：在一个实施例中，多处理装置包括第一处理器和第二处理器。每个处理器都有自己的数据和指令高速缓存来支持独立操作。在正常模式下，处理器独立地执行单独的指令流。每个处理器具有相应的签名生成器。该系统还包括耦合到签名生成器的比较单元。在高可靠性模式下，两个处理器执行相同的指令流。也就是说，每个处理器计算流中的指令的结果的版本。响应于各自的版本，相应的签名生成器向比较单元提供签名，从而可以检测到故障指令。在另一方面，每个处理器具有其各自的提交逻辑。一旦比较单元接收到相应版本的结果的签名，但只有当签名匹配时，比较单元才会发信号通知每个相应处理器中的提交逻辑已经消除了该指令产生的计算中断的可能性。这允许提交逻辑提交结果。如果签名不匹配，则比较单元向提交逻辑发出相应指令发生故障的信号。提交逻辑允许以程序顺序执行故障指令之前的指令继续执行，但是启动由故障指令产生的结果和程序顺序中的至少一些指令冲洗到故障指令。

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