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81. 发明申请

US20110208907A1 Protected Cache Architecture And Secure Programming Paradigm To Protect Applications 有权
标题翻译：保护缓存架构和安全编程范例来保护应用程序
公开(公告)号：US20110208907A1
公开(公告)日：2011-08-25
申请号：US13099479
申请日：2011-05-03
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F12/06 , G06F12/08
CPC分类号： G06F12/0802 , G06F12/0804 , G06F12/1491 , G06F21/10
摘要： Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种安全编程范例和受保护的高速缓存，其使得处理器能够处理秘密/专用信息，同时防止恶意应用程序通过规避其他保护机制来访问该信息。受保护的缓存可以用作构建块，以增强试图创建，管理和保护安全数据的应用程序的安全性。描述和要求保护其他实施例。

82. 发明申请

US20100011193A1 Selective Hardware Lock Disabling 有权
标题翻译：选择性硬件锁定禁用
公开(公告)号：US20100011193A1
公开(公告)日：2010-01-14
申请号：US12562457
申请日：2009-09-18
申请人： Shlomo Raikin , Gad Sheaffer , Doron Orenstlen
发明人： Shlomo Raikin , Gad Sheaffer , Doron Orenstlen
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/526
摘要： Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.
摘要翻译：描述了控制重排序缓冲器（ROB）以选择性地执行功能性硬件锁定禁止（HLD）。一个设备实施例包括一个单元，以使得ROB能够在识别与关键部分（CS）入口点相关联的锁定获取操作（LAO）时选择性地禁用锁定，该选择单元选择性地退出LAO，该单元使得ROB 选择性地禁用该锁，以及一个单元来窥探缓冲区。该设备可以基于窥探，选择性地中止与CS相关联的事务。

83. 发明授权

US07613908B2 Selective hardware lock disabling 有权
标题翻译：选择性硬件锁定禁用
公开(公告)号：US07613908B2
公开(公告)日：2009-11-03
申请号：US11710028
申请日：2007-02-23
申请人： Shlomo Raikin , Gad Sheaffer , Doron Orenstien
发明人： Shlomo Raikin , Gad Sheaffer , Doron Orenstien
IPC分类号： G06F9/312
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/526
摘要： Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.
摘要翻译：描述了控制重排序缓冲器（ROB）以选择性地执行功能性硬件锁定禁止（HLD）。一个设备实施例包括一个单元，以使得ROB能够在识别与关键部分（CS）入口点相关联的锁定获取操作（LAO）时选择性地禁用锁定，该选择单元选择性地退出LAO，该单元使得ROB 选择性地禁用该锁，以及一个单元来窥探缓冲区。该设备可以基于窥探，选择性地中止与CS相关联的事务。

84. 发明申请

US20080147992A1 Protecting Private Data from Cache Attacks 有权
标题翻译：保护私密数据免受缓存攻击
公开(公告)号：US20080147992A1
公开(公告)日：2008-06-19
申请号：US11950963
申请日：2007-12-05
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F12/00
CPC分类号： G06F12/0833 , G06F12/1416 , G06F21/554 , G06F2221/2143
摘要： A method for protecting private data from cache attacks is disclosed. One embodiment includes storing private data in a protected cache line to protect it from cache attacks, receiving a snoop request to the protected cache line, and responding to the snoop request with a miss.
摘要翻译：公开了一种保护私有数据免受高速缓存攻击的方法。一个实施例包括将私有数据存储在受保护的高速缓存行中以保护其免受高速缓存攻击，向受保护的高速缓存行接收窥探请求，以及错过响应窥探请求。

85. 发明授权

US06976049B2 Method and apparatus for implementing single/dual packed multi-way addition instructions having accumulation options 有权
标题翻译：用于实现具有累积选项的单/双包装多路加法指令的方法和装置
公开(公告)号：US06976049B2
公开(公告)日：2005-12-13
申请号：US10107257
申请日：2002-03-28
申请人： Gad Sheaffer
发明人： Gad Sheaffer
IPC分类号： G06F7/50 , G06F7/509 , G06F9/30 , G06F9/302 , G06F9/32 , G06F9/38 , G06F15/00
CPC分类号： G06F9/30094 , G06F7/509 , G06F9/3001 , G06F9/30036 , G06F9/30145 , G06F9/3875 , G06F9/3885
摘要： The present invention relates to a method and system for providing a single accumulatable packed multi-way addition instruction having the functionality of multiple instructions without causing any timing problems in the execute stage. Specifically, the accumulatable packed multi-way combination instruction may be associated with at least one destination and a plurality of operands and set a polarity of each of a plurality of source operands derived from the plurality of operands, if requested by the instruction. The instruction also may add selected pairs of the plurality of source operands in predetermined orders to obtain at least one result and, if requested by the instruction, accumulating the plurality of results to obtain at least one accumulated result; output at least one predetermined pair of the at least one result and the at least one accumulated result; and accumulate condition codes for each of the at least one result and the at least one accumulated result, if requested by the instruction.
摘要翻译：本发明涉及一种用于提供具有多个指令的功能的单个可累积的打包多路加法指令的方法和系统，而不会在执行阶段中引起任何定时问题。具体地，如果该指令请求，则可累加的打包多路组合指令可以与至少一个目的地和多个操作数相关联，并且设置从多个操作数导出的多个源操作数中的每一个的操作数的极性。指令还可以按预定顺序添加多个源操作数的选定对，以获得至少一个结果，并且如果该指令请求，则累积多个结果以获得至少一个累积结果; 输出所述至少一个结果和所述至少一个累积结果中的至少一个预定对; 以及如果所述指令请求，则对于所述至少一个结果中的每一个和所述至少一个累加结果累加条件代码。

86. 发明申请

US20050149697A1 Mechanism to exploit synchronization overhead to improve multithreaded performance 有权
标题翻译：利用同步开销来提高多线程性能的机制
公开(公告)号：US20050149697A1
公开(公告)日：2005-07-07
申请号：US11070991
申请日：2005-03-02
申请人： Natalie Enright , Jamison Collins , Perry Wang , Hong Wang , Xinmin Tran , John Shen , Gad Sheaffer , Per Hammarlund
发明人： Natalie Enright , Jamison Collins , Perry Wang , Hong Wang , Xinmin Tran , John Shen , Gad Sheaffer , Per Hammarlund
IPC分类号： G06F9/30 , G06F9/38 , G06F9/48 , G06F11/34
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/4843 , G06F11/3419 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and an event detector to detect a long latency event associated with a synchronization object. The event detector can cause a first thread switch in response to the long latency event associated with the synchronization object. The apparatus may also include a spin detector to detect that the synchronization object is a contended synchronization object. The spin detector can cause a second thread switch in response to the detection of the contended synchronization object to enable a spin detect response.
摘要翻译：用于可激活其他线程的可编程事件驱动产量机制的方法，装置和程序装置。在一个实施例中，装置包括执行多个指令的执行资源和用于检测与同步对象相关联的长延迟事件的事件检测器。事件检测器可以响应于与同步对象相关联的长等待时间事件而导致第一线程切换。该装置还可以包括检测同步对象是竞争同步对象的自旋检测器。响应于竞争的同步对象的检测，自旋检测器可以引起第二线程切换以启用自旋检测响应。

87. 发明授权

US09164923B2 Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform 有权
标题翻译：动态固定异构计算平台的不同类型处理器之间共享的虚拟页面
公开(公告)号：US09164923B2
公开(公告)日：2015-10-20
申请号：US13175489
申请日：2011-07-01
申请人： Gad Sheaffer , Boris Ginzburg , Ronny Ronen , Eliezer Weissmann
发明人： Gad Sheaffer , Boris Ginzburg , Ronny Ronen , Eliezer Weissmann
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12
CPC分类号： G06F12/1027 , G06F12/0804 , G06F12/126 , G06F13/1663 , G06F2212/303 , G06F2212/657 , G06F2212/684
摘要： A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device (e.g., a graphics processing unit, GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. In one embodiment, the device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.
摘要翻译：计算机系统可以支持一种或多种技术来允许由非CPU设备（例如，图形处理单元，GPU）访问的存储器页的动态固定。非CPU可以支持虚拟到物理地址映射，并且因此可以知道可能不被固定但可被非CPU访问的存储器页。非CPU可以向诸如与CPU相关联的设备驱动程序的运行时组件通知或发送这样的信息。在一个实施例中，设备驱动程序可以动态地执行可由非CPU访问的这种存储器页的钉扎。设备驱动程序甚至可以取消内存页，这可能不再被非CPU访问。这样的方法可以允许非CPU可以不再访问的存储器页面可用于分配给其他CPU和/或非CPU。

88. 发明授权

US08769212B2 Memory model for hardware attributes within a transactional memory system 有权
标题翻译：事务内存系统中硬件属性的内存模型
公开(公告)号：US08769212B2
公开(公告)日：2014-07-01
申请号：US13359238
申请日：2012-01-26
申请人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
发明人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/3838 , G06F11/0715 , G06F11/0724 , G06F11/073 , G06F11/0751 , G06F11/3017 , G06F11/3037 , G06F11/3089 , G06F11/3471 , G06F12/0831 , G06F12/084 , G06F2201/885
摘要： A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.
摘要翻译：这里描述了一种用于提供用于硬件属性以支持事务执行的存储器模型的方法和装置。在遇到诸如加载读取监视器，写入监视器或缓冲属性的测试监视器操作的硬件属性的负载时，响应于指示硬件属性已经丢失的丢失字段而发出故障。此外，基于地址依赖性和访问类型依赖性，为属性访问操作提供依赖操作，例如阻塞和转发。因此，在存储器模型中允许和限制属性丢失和测试的不同场景。

89. 发明授权

US08627014B2 Memory model for hardware attributes within a transactional memory system 有权
公开(公告)号：US08627014B2
公开(公告)日：2014-01-07
申请号：US12346539
申请日：2008-12-30
申请人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
发明人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
IPC分类号： G06F12/08
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/3838 , G06F11/0715 , G06F11/0724 , G06F11/073 , G06F11/0751 , G06F11/3017 , G06F11/3037 , G06F11/3089 , G06F11/3471 , G06F12/0831 , G06F12/084 , G06F2201/885
摘要： A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.

90. 发明授权

US08209689B2 Live lock free priority scheme for memory transactions in transactional memory 有权
标题翻译：事务内存中的内存事务的实时锁定优先级方案
公开(公告)号：US08209689B2
公开(公告)日：2012-06-26
申请号：US11854175
申请日：2007-09-12
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F9/52 , G06F13/14 , G06F12/00 , G06F7/00 , G06F13/00
CPC分类号： G06F9/524 , G06F9/466
摘要： A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value. When the FMV counter is at a predetermined number of aborts the counting logic is reset to avoid live lock.
摘要翻译：这里描述了用于在事务执行期间避免实时锁定的方法和装置。计数逻辑用于跟踪每个处理元素的成功提交事务。当在多个处理元件之间的事务之间检测到数据冲突时，以较低的计数逻辑值提供给处理元件的优先级。此外，如果值相同，则具有较低识别值的处理元件被赋予优先级，即允许在其他事务被中止时继续。为了避免在具有预定的计数逻辑值（例如最大计数值）的处理元件之间的实时锁定，当一个处理元件达到预定计数值时，所有计数器都被重置。此外，当计数逻辑处于最大值时，可以提供在最大值（FMV）计数器上的故障来计数事务的中止次数。当FMV计数器处于预定数量的中止时，计数逻辑被复位以避免实时锁定。

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