专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20130024752A1 MEMORY CELL SUPPLY VOLTAGE CONTROL BASED ON ERROR DETECTION 有权
标题翻译：基于错误检测的存储单元电源电压控制
公开(公告)号：US20130024752A1
公开(公告)日：2013-01-24
申请号：US13626435
申请日：2012-09-25
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G06F11/07
CPC分类号： G11C29/42 , G11C11/4125 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004
摘要： Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.
摘要翻译：这里描述了一种用于调整存储器单元的电源电平以提高存储器单元的稳定性的装置。该装置包括存储器电路，其包括存储器单元，用于检测由存储器电路的存储器单元存储的数据中的错误的误差检测电路，以及供应电压控制电路，用于至少部分地增加存储器电路的一个或多个存储器单元的电源电压检测到错误。

82. 发明授权

US08006164B2 Memory cell supply voltage control based on error detection 有权
标题翻译：基于错误检测的存储单元电源电压控制
公开(公告)号：US08006164B2
公开(公告)日：2011-08-23
申请号：US11542007
申请日：2006-09-29
申请人： Khellah Muhammad , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Khellah Muhammad , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/4125 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004
摘要： For one embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments have one or more other features.
摘要翻译：对于一个实施例，一种装置包括存储器电路，其包括存储器单元，用于检测由存储器电路的存储器单元存储的数据中的错误的错误检测电路，以及用于增加基于存储器电路的一个或多个存储器单元的电源电压的电源电压控制电路至少部分是检测到的错误。其他实施例具有一个或多个其他特征。

83. 发明申请

US20070002611A1 Operating an information storage cell array 有权
公开(公告)号：US20070002611A1
公开(公告)日：2007-01-04
申请号：US11172742
申请日：2005-06-30
申请人： Yibin Ye , Muhammad Khellah , Dinesh Somasekhar , Ali Keshavarzi , Fabrice Paillet , Vivek De
发明人： Yibin Ye , Muhammad Khellah , Dinesh Somasekhar , Ali Keshavarzi , Fabrice Paillet , Vivek De
IPC分类号： G11C11/34
CPC分类号： G11C11/405 , G11C7/062 , G11C7/067 , G11C7/12 , G11C11/4085 , G11C11/4091 , G11C11/4094
摘要： A cell in an information storage cell array is written, by asserting a signal on a bit line that is coupled to the cell and to a group of other cells in the array, to a first voltage. The cell is read by asserting a signal on a word line that is coupled to the cell and to another group of cells in the array, in a direction of, but without reaching, the first voltage. Other embodiments are also described and claimed.

84. 发明申请

US20060054933A1 Asymmetric memory cell 有权
公开(公告)号：US20060054933A1
公开(公告)日：2006-03-16
申请号：US11268098
申请日：2005-11-07
申请人： Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： H01L27/10
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L29/7841
摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

85. 发明申请

US20060002211A1 Two transistor gain cell, method, and system 有权
公开(公告)号：US20060002211A1
公开(公告)日：2006-01-05
申请号：US10881001
申请日：2004-06-30
申请人： Yibin Ye , Dinesh Somasekhar , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek De
发明人： Yibin Ye , Dinesh Somasekhar , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek De
IPC分类号： G11C7/00
CPC分类号： G11C11/405
摘要： A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.

86. 发明申请

US20050213370A1 SRAM WITH FORWARD BODY BIASING TO IMPROVE READ CELL STABILITY 有权
标题翻译：具有前向体积偏移以提高读取单元稳定性的SRAM
公开(公告)号：US20050213370A1
公开(公告)日：2005-09-29
申请号：US10810093
申请日：2004-03-26
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Ali Farhang , Gunjan Pandya , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Ali Farhang , Gunjan Pandya , Vivek De
IPC分类号： G11C11/41 , G11C11/419
CPC分类号： G11C11/419
摘要： A SRAM memory cell comprising cross-coupled inverters, each cross-coupled inverter comprising a pull-up transistor, where the pull-up transistors are forward body biased during read operations. Forward body biasing improves the read stability of the memory cell. Other embodiments are described and claimed.
摘要翻译：一种SRAM存储单元，包括交叉耦合的反相器，每个交叉耦合的反相器包括一个上拉晶体管，其中上拉晶体管在读取操作期间被正向偏置。正向主体偏置改善了存储单元的读取稳定性。描述和要求保护其他实施例。

87. 发明申请

US20050146956A1 BITE-LINE DROOP REDUCTION 失效
标题翻译： BINE-LINE DROOP减少
公开(公告)号：US20050146956A1
公开(公告)日：2005-07-07
申请号：US10746148
申请日：2003-12-24
申请人： Dinesh Somasekhar , Yibin Ye , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek De
发明人： Dinesh Somasekhar , Yibin Ye , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek De
IPC分类号： G11C7/00 , G11C7/12
CPC分类号： G11C7/12
摘要： Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.
摘要翻译：一些实施例使用预充电器件将耦合到存储器单元的位线预充电至参考电压，基于存储器单元存储的值，放电期间的注入，放电期间的位线放电，使用预充电器件进入位线的第一电流，以及在放电期间使用第二预充电器件将第二电流注入参考位线。此外，在放电期间，在位线上的电压和参考位线上的电压之间感测到差异。

88. 发明申请

US20050111255A1 Floating-body dynamic random access memory with purge line 失效
标题翻译：具有清除线的浮动动态随机存取存储器
公开(公告)号：US20050111255A1
公开(公告)日：2005-05-26
申请号：US10721184
申请日：2003-11-26
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： G11C11/404 , H01L27/108 , G11C11/34
CPC分类号： H01L27/108 , G11C11/404
摘要： Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.
摘要翻译：实施例涉及浮体动态随机存取存储器（FBDRAM）。在将数据写入FBDRAM单元之前，FBDRAM利用清除线来复位FBDRAM单元。

89. 发明授权

US06316960B2 Domino logic circuit and method 失效
标题翻译：多米诺逻辑电路和方法
公开(公告)号：US06316960B2
公开(公告)日：2001-11-13
申请号：US09286914
申请日：1999-04-06
申请人： Yibin Ye
发明人： Yibin Ye
IPC分类号： H03K19096
CPC分类号： H03K19/096
摘要： A domino logic circuit includes input connections to receive a clock signal and an input data signal. In one embodiment, the domino logic circuit includes a dynamic stage comprising at least one n-channel pull-up transistor having a gate coupled to receive the input data signal. The n-channel pull-up transistor has a low threshold voltage. The dynamic stage can include an n-channel pull-down transistor which has a gate connection coupled to receive the clock signal. First and second inverter circuits can also be provided to latch a voltage on a drain of the pull-down transistor. Static logic circuits coupled to the dynamic stage have skewed rise and fall times to increase the propagation time of the domino circuit.
摘要翻译：多米诺逻辑电路包括用于接收时钟信号和输入数据信号的输入连接。在一个实施例中，多米诺逻辑电路包括动态级，其包括至少一个n沟道上拉晶体管，其具有耦合以接收输入数据信号的栅极。 n沟道上拉晶体管具有低阈值电压。动态级可以包括n沟道下拉晶体管，其具有耦合以接收时钟信号的栅极连接。还可以提供第一和第二反相器电路以锁存下拉晶体管的漏极上的电压。耦合到动态级的静态逻辑电路具有偏斜的上升和下降时间，以增加多米诺骨电路的传播时间。

90. 发明授权

US08769376B2 Memory cell supply voltage control based on error detection 有权
公开(公告)号：US08769376B2
公开(公告)日：2014-07-01
申请号：US13626435
申请日：2012-09-25
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/4125 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004
摘要： Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式