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81. 发明授权

US08440490B2 CMOS imager photodiode with enhanced capacitance 有权
标题翻译：具有增强电容的CMOS成像光电二极管
公开(公告)号：US08440490B2
公开(公告)日：2013-05-14
申请号：US13288686
申请日：2011-11-03
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
IPC分类号： H01L31/18
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14689 , H01L31/035281
摘要： A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface.
摘要翻译：一种制造像素传感器单元的方法，该像素传感器单元包括具有非横向放置的电荷收集区域的感光元件。该方法包括在第一导电类型材料的衬底中形成沟槽凹槽，并用具有第二导电类型材料的材料填充沟槽凹槽。然后将第二导电类型材料从填充的沟槽材料扩散到围绕沟槽的衬底区域，以形成非横向布置的电荷收集区域。去除填充的沟槽材料以提供沟槽凹槽，并且用具有第一导电类型材料的材料填充沟槽凹槽。表面注入层形成在具有第一导电类型材料的沟槽的任一侧。沟槽型感光元件的收集区域由向外扩散的第二导电型材料形成，并与衬底表面隔离。

82. 发明申请

US20090236644A1 HIGH EFFICIENCY CMOS IMAGE SENSOR PIXEL EMPLOYING DYNAMIC VOLTAGE SUPPLY 有权
标题翻译：高效CMOS图像传感器像素采用动态电压供应
公开(公告)号：US20090236644A1
公开(公告)日：2009-09-24
申请号：US12050967
申请日：2008-03-19
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
IPC分类号： H01L31/113 , H04N5/335 , G06F17/50
CPC分类号： H04N5/361 , G06F17/5063 , H04N5/359 , H04N5/3745
摘要： A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.
摘要翻译：提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少在信号保持时间期间浮动扩散时的电压变化。此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

83. 发明申请

US20120122261A1 CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 有权
标题翻译：具有增强电容的CMOS IMAGER光电二极管
公开(公告)号：US20120122261A1
公开(公告)日：2012-05-17
申请号：US13288686
申请日：2011-11-03
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
IPC分类号： H01L31/18
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14689 , H01L31/035281
摘要： A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface.
摘要翻译：一种制造像素传感器单元的方法，该像素传感器单元包括具有非横向放置的电荷收集区域的感光元件。该方法包括在第一导电类型材料的衬底中形成沟槽凹槽，并用具有第二导电类型材料的材料填充沟槽凹槽。然后将第二导电类型材料从填充的沟槽材料扩散到围绕沟槽的衬底区域，以形成非横向布置的电荷收集区域。去除填充的沟槽材料以提供沟槽凹槽，并且用具有第一导电类型材料的材料填充沟槽凹槽。表面注入层形成在具有第一导电类型材料的沟槽的任一侧。沟槽型感光元件的收集区域由向外扩散的第二导电型材料形成，并与衬底表面隔离。

84. 发明申请

US20100097511A1 HIGH EFFICIENCY CMOS IMAGE SENSOR PIXEL EMPLOYING DYNAMIC VOLTAGE SUPPLY 失效
标题翻译：高效CMOS图像传感器像素采用动态电压供应
公开(公告)号：US20100097511A1
公开(公告)日：2010-04-22
申请号：US12641589
申请日：2009-12-18
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
IPC分类号： H04N5/335 , G06F17/50
CPC分类号： H04N5/361 , G06F17/5063 , H04N5/359 , H04N5/3745
摘要： A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.
摘要翻译：提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

85. 发明授权

US07141836B1 Pixel sensor having doped isolation structure sidewall 有权
标题翻译：具有掺杂隔离结构侧壁的像素传感器
公开(公告)号：US07141836B1
公开(公告)日：2006-11-28
申请号：US10908885
申请日：2005-05-31
申请人： James W. Adkisson , Mark D. Jaffe , Robert K. Leidy
发明人： James W. Adkisson , Mark D. Jaffe , Robert K. Leidy
IPC分类号： H01L27/148
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14683
摘要： A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. An isolation structure is formed adjacent to the photosensitive device pinning layer. The isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the isolation structure are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material.
摘要翻译：形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成隔离结构。隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散工艺，由此在退火期间，存在于沿隔离结构中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来执行。

86. 发明授权

US08106432B2 CMOS imager photodiode with enhanced capacitance 有权
标题翻译：具有增强电容的CMOS成像光电二极管
公开(公告)号：US08106432B2
公开(公告)日：2012-01-31
申请号：US12634898
申请日：2009-12-10
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
IPC分类号： H01L31/04
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14689 , H01L31/035281
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.
摘要翻译：一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间并形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离，基材表面。在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于在衬底表面形成的掺杂层的下方。

87. 发明授权

US08023021B2 High efficiency CMOS image sensor pixel employing dynamic voltage supply 失效
标题翻译：采用动态电压源的高效率CMOS图像传感器像素
公开(公告)号：US08023021B2
公开(公告)日：2011-09-20
申请号：US12641589
申请日：2009-12-18
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
IPC分类号： H04N5/335
CPC分类号： H04N5/361 , G06F17/5063 , H04N5/359 , H04N5/3745
摘要： A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.
摘要翻译：提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

88. 发明申请

US20100136733A1 SILICIDE STRAPPING IN IMAGER TRANSFER GATE DEVICE 有权
标题翻译：图像转印门装置中的硅胶缠绕
公开(公告)号：US20100136733A1
公开(公告)日：2010-06-03
申请号：US12699419
申请日：2010-02-03
申请人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
发明人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
IPC分类号： H01L31/18
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689
摘要： A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.
摘要翻译：具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

89. 发明授权

US07659564B2 CMOS imager photodiode with enhanced capacitance 失效
标题翻译：具有增强电容的CMOS成像光电二极管
公开(公告)号：US07659564B2
公开(公告)日：2010-02-09
申请号：US11276085
申请日：2006-02-14
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
IPC分类号： H01L31/04
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14689 , H01L31/035281
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.
摘要翻译：一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间并形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离，基材表面。在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于在衬底表面形成的掺杂层的下方。

90. 发明授权

US07194706B2 Designing scan chains with specific parameter sensitivities to identify process defects 失效
标题翻译：设计具有特定参数灵敏度的扫描链，以识别过程缺陷
公开(公告)号：US07194706B2
公开(公告)日：2007-03-20
申请号：US10710642
申请日：2004-07-27
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Leendert M. Huisman , Mark D. Jaffe , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak , David E. Sweenor , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Leendert M. Huisman , Mark D. Jaffe , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak , David E. Sweenor , David P. Vallett
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划确定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

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