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81. 发明申请

US20050048794A1 Method for making a semiconductor device having a high-k gate dielectric 失效
公开(公告)号：US20050048794A1
公开(公告)日：2005-03-03
申请号：US10652796
申请日：2003-08-28
申请人： Justin Brask , Mark Doczy , Scott Hareland , John Barnak , Matthew Metz , Jack Kavalieros , Robert Chau
发明人： Justin Brask , Mark Doczy , Scott Hareland , John Barnak , Matthew Metz , Jack Kavalieros , Robert Chau
IPC分类号： H01L21/28 , H01L21/30 , H01L21/306 , H01L21/316 , H01L29/51 , H01L21/336 , H01L21/3205 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02244 , H01L21/02052 , H01L21/02337 , H01L21/0234 , H01L21/28167 , H01L21/28194 , H01L21/3003 , H01L21/31612 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31683 , H01L21/31691 , H01L29/513 , H01L29/517
摘要： A method for making a semiconductor device is described. That method comprises forming a metal oxide layer on a substrate, converting at least part of the metal oxide layer to a metal layer; and oxidizing the metal layer to generate a metal oxide high-k gate dielectric layer.

82. 发明申请

US20050272191A1 Replacement gate process for making a semiconductor device that includes a metal gate electrode 审中-公开
标题翻译：用于制造包括金属栅电极的半导体器件的替代栅极工艺
公开(公告)号：US20050272191A1
公开(公告)日：2005-12-08
申请号：US10861727
申请日：2004-06-03
申请人： Uday Shah , Mark Doczy , Justin Brask , Jack Kavalieros , Matthew Metz , Robert Chau , Chris Barns
发明人： Uday Shah , Mark Doczy , Justin Brask , Jack Kavalieros , Matthew Metz , Robert Chau , Chris Barns
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/338 , H01L21/8234 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66583 , H01L29/7833
摘要： A method for making a semiconductor device is described. That method comprises forming a sacrificial layer on a substrate, and forming a trench within the sacrificial layer. After forming a dummy gate electrode within the trench, a hard mask is formed on the dummy gate electrode and within the trench.
摘要翻译：描述制造半导体器件的方法。该方法包括在衬底上形成牺牲层，以及在牺牲层内形成沟槽。在沟槽内形成虚拟栅电极之后，在伪栅电极和沟槽内形成硬掩模。

83. 发明申请

US20050202644A1 Method for fabricating metal gate structures 有权
标题翻译：金属栅极结构的制造方法
公开(公告)号：US20050202644A1
公开(公告)日：2005-09-15
申请号：US11120353
申请日：2005-05-02
申请人： Mark Doczy , Mark Liu , Jack Kavalieros , Justin Brask , Matthew Metz , Robert Chau
发明人： Mark Doczy , Mark Liu , Jack Kavalieros , Justin Brask , Matthew Metz , Robert Chau
IPC分类号： H01L21/268 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/00 , H01L21/84
CPC分类号： H01L29/495 , H01L21/268 , H01L21/823828 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66575 , H01L29/6659
摘要： Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate.
摘要翻译：描述形成微电子结构的方法。这些方法包括提供包括源极/漏极和栅极区域的衬底，其中栅极区域包括设置在栅极介电层上的金属层，然后激光退火衬底。

84. 发明申请

US20050101134A1 Method for etching a thin metal layer 失效
标题翻译：蚀刻薄金属层的方法
公开(公告)号：US20050101134A1
公开(公告)日：2005-05-12
申请号：US10704498
申请日：2003-11-06
申请人： Justin Brask , Mark Doczy , Jack Kavalieros , Uday Shah , Matthew Metz , Robert Chau , Robert Turkot
发明人： Justin Brask , Mark Doczy , Jack Kavalieros , Uday Shah , Matthew Metz , Robert Chau , Robert Turkot
IPC分类号： C23F1/02 , H01L21/3213 , H01L21/8238 , H01L21/302 , H01L21/461
CPC分类号： C23F1/02 , H01L21/32134 , H01L21/823842
摘要： A method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer.
摘要翻译：描述了蚀刻金属层的方法。该方法包括在基底上形成金属层，然后将金属层的一部分暴露于包含直径超过金属层厚度的活性成分的湿式蚀刻化学物质。

85. 发明申请

US20070152271A1 Gate electrode having a capping layer 有权
标题翻译：栅极具有封盖层
公开(公告)号：US20070152271A1
公开(公告)日：2007-07-05
申请号：US11322745
申请日：2005-12-30
申请人： Gilbert Dewey , Mark Doczy , Suman Datta , Justin Brask , Matthew Metz
发明人： Gilbert Dewey , Mark Doczy , Suman Datta , Justin Brask , Matthew Metz
IPC分类号： H01L21/8234 , H01L21/336 , H01L29/76
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28194 , H01L21/823828 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66795 , H01L29/78
摘要： A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
摘要翻译：本文公开了半导体器件和新型半导体器件的制造方法。示例性的方法包括在执行任何高温处理步骤之前，在栅介质层上原位溅射覆盖层。

86. 发明申请

US20050095792A1 Depositing an oxide 失效
标题翻译：沉积氧化物
公开(公告)号：US20050095792A1
公开(公告)日：2005-05-05
申请号：US10696204
申请日：2003-10-29
申请人： Ying Zhou , Matthew Metz , Justin Brask , John Burghard , Markus Kuhn , Suman Datta , Robert Chau
发明人： Ying Zhou , Matthew Metz , Justin Brask , John Burghard , Markus Kuhn , Suman Datta , Robert Chau
IPC分类号： H01L21/316 , H01L21/3205 , H01L21/336 , H01L21/76 , H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02282 , H01L21/02164 , H01L21/02181 , H01L21/02189 , H01L21/022 , H01L21/316
摘要： A dielectric deposited on a substrate may be exposed to a salt solution. While exposed to the salt solution, an oxide is deposited on the dielectric.
摘要翻译：沉积在基底上的电介质可以暴露于盐溶液中。当暴露于盐溶液时，在电介质上沉积氧化物。

87. 发明申请

US20070158702A1 Transistor including flatband voltage control through interface dipole engineering 审中-公开
标题翻译：晶体管包括通过接口偶极工程的平带电压控制
公开(公告)号：US20070158702A1
公开(公告)日：2007-07-12
申请号：US11322827
申请日：2005-12-30
申请人： Mark Doczy , Matthew Metz , Justin Brask , Robert Chau , Gilbert Dewey
发明人： Mark Doczy , Matthew Metz , Justin Brask , Robert Chau , Gilbert Dewey
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/785 , H01L29/4908
摘要： A transistor comprising a semiconductor including a source, a drain, and a channel interposed between the source and the drain; a first dielectric layer having a first thickness, the first dielectric layer being positioned on the channel; a second dielectric layer having a second thickness, the second dielectric layer being positioned on the first dielectric layer; and a gate electrode on the second dielectric layer, wherein the transistor gate is made of a mid-gap metal. A process comprising depositing a first dielectric layer on at least one surface of a semiconductor layer; depositing a second dielectric layer on the first dielectric layer; depositing a layer of mid-gap metal on the second dielectric layer; and patterning and etching the first dielectric layer, the second dielectric layer and the layer of mid-gap metal to create a gate electrode separated from the substrate by a first dielectric and a second dielectric. Other embodiments are disclosed and claimed.
摘要翻译：一种晶体管，包括：半导体，包括源极，漏极和介于源极和漏极之间的沟道; 具有第一厚度的第一介电层，所述第一介电层位于所述通道上; 具有第二厚度的第二介电层，所述第二介电层位于所述第一介电层上; 以及第二介质层上的栅电极，其中晶体管栅极由中间间隙金属制成。一种方法，包括在半导体层的至少一个表面上沉积第一介电层; 在所述第一电介质层上沉积第二电介质层; 在所述第二电介质层上沉积中间间隙金属层; 以及对第一电介质层，第二电介质层和中间间隙金属层进行图案化和蚀刻以产生通过第一电介质和第二电介质与衬底分离的栅电极。公开和要求保护其他实施例。

88. 发明申请

US20070145498A1 DEVICE WITH SCAVENGING SPACER LAYER 有权
标题翻译：装置与SCAVENGING间隔层
公开(公告)号：US20070145498A1
公开(公告)日：2007-06-28
申请号：US11320305
申请日：2005-12-27
申请人： Matthew Metz , Mark Doczy , Justin Brask , Robert Chau
发明人： Matthew Metz , Mark Doczy , Justin Brask , Robert Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/0847 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66636
摘要： Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen-scavenging spacer layer on side walls of the high-k gate dielectric layer and metal gate may reduce such oxidation during high temperature processes.
摘要翻译：本发明的实施例提供一种具有金属栅极，高k栅极电介质层和在高k栅极电介质层下面的衬底的氧化减少的器件。在高k栅极电介质层和金属栅极的侧壁上的氧气清除间隔层可以在高温过程中减少这种氧化。

89. 发明授权

US09048314B2 Field effect transistor with narrow bandgap source and drain regions and method of fabrication 有权
公开(公告)号：US09048314B2
公开(公告)日：2015-06-02
申请号：US14465636
申请日：2014-08-21
申请人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
发明人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
IPC分类号： H01L29/66 , H01L29/78 , H01L29/786 , H01L29/267 , H01L29/10 , H01L29/20 , H01L29/423 , H01L29/51
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/16 , H01L29/20 , H01L29/201 , H01L29/207 , H01L29/267 , H01L29/41783 , H01L29/4236 , H01L29/452 , H01L29/517 , H01L29/66522 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7827 , H01L29/7836 , H01L29/785 , H01L29/78603 , H01L29/78618 , H01L29/78681
摘要： A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

90. 发明申请

US20130146945A1 FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION 有权
公开(公告)号：US20130146945A1
公开(公告)日：2013-06-13
申请号：US13752272
申请日：2013-01-28
申请人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
发明人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
IPC分类号： H01L29/267
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/16 , H01L29/20 , H01L29/201 , H01L29/207 , H01L29/267 , H01L29/41783 , H01L29/4236 , H01L29/452 , H01L29/517 , H01L29/66522 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7827 , H01L29/7836 , H01L29/785 , H01L29/78603 , H01L29/78618 , H01L29/78681
摘要： A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

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