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    • 81. 发明申请
    • Digital-to-Analog Conversion Circuit
    • 数模转换电路
    • US20100265112A1
    • 2010-10-21
    • US12423991
    • 2009-04-15
    • Staffan EkStefan Andersson
    • Staffan EkStefan Andersson
    • H03M1/66
    • H03M1/662H03M1/0678H03M1/08H03M1/687H03M3/504
    • A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC), a second DAC, and a control circuit to select which DAC to use for digital-to-analog conversion of a digital signal. Concerned with the noise level produced at a given out-of-band frequency, the control circuit bases its selection of DACs, at least in part, on a frequency distance between the given out-of-band frequency and the digital signal's frequency. The control circuit, for example, may select the DAC producing the lowest noise level at that frequency distance, or, if both DACs are able to reduce noise to a level below a noise tolerance specified for the frequency distance, the DAC consuming the least power. To reduce the chip area required for the digital-to-analog conversion circuit, the first and second DACs advantageously have topologies that permit them to share common components (e.g., DAC unit elements).
    • 数模转换电路包括第一数模转换器(DAC),第二DAC和控制电路,以选择要用于数字信号的数模转换的DAC。 关于在给定的带外频率下产生的噪声电平,控制电路至少部分地基于给定的带外频率和数字信号频率之间的频率距离来选择DAC。 例如,控制电路可以选择在该频率距离处产生最低噪声电平的DAC,或者如果两个DAC能够将噪声降低到低于针对频率距离指定的噪声容限的水平,则DAC消耗最小功率 。 为了减少数模转换电路所需的芯片面积,第一和第二DAC有利地具有允许它们共享公共部件(例如,DAC单元元件)的拓扑。
    • 84. 发明申请
    • Adaptive Bit Allocation for Multi-Channel Audio Encoding
    • 适用于多通道音频编码的位分配
    • US20080262850A1
    • 2008-10-23
    • US11816996
    • 2005-12-22
    • Anisse TalebStefan Andersson
    • Anisse TalebStefan Andersson
    • G10L19/00
    • G10L19/008G10L19/24
    • The invention provides a highly efficient technique for encoding a multi-channel audio signal. The invention relies on the basic principle of encoding a first signal representation of one or more of the multiple channels in a first encoder (130) and encoding a second signal representation of one or more of the multiple channels in a second, multi-stage, encoder (140). This procedure is significantly enhanced by providing a controller (150) for adaptively allocating a number of encoding bits among the different encoding stages of the second, multi-stage, encoder (140) in dependence on multi-channel audio signal characteristics.
    • 本发明提供了一种用于编码多声道音频信号的高效技术。 本发明依赖于在第一编码器(130)中编码多个信道中的一个或多个信道的第一信号表示的基本原理,并且在第二多级信道中编码多个信道中的一个或多个信道的第二信号表示, 编码器(140)。 通过提供一种用于根据多声道音频信号特性在第二,多级编码器(140)的不同编码级之间自适应地分配多个编码位的控制器(150)来显着增强该过程。
    • 88. 发明申请
    • SECURE DIGITAL CERTIFICATE STORING SCHEME FOR FLASH MEMORY AND ELECTRONIC APPARATUS
    • 闪存和电子设备的安全数字证书存储方案
    • US20070130439A1
    • 2007-06-07
    • US11164673
    • 2005-12-01
    • Stefan AnderssonWerner JohanssonStefan Lindgren
    • Stefan AnderssonWerner JohanssonStefan Lindgren
    • G11C7/00
    • G06F21/575G06F21/79G11C16/22
    • The invention relates generally to data security and to data memory technologies, and more specifically provides a method for storing and updating digital certificates in a flash memory, and provides further a flash memory and an electronic apparatus exploiting said method. The method according to the invention is applicable for a flash memory (110) having predefined erase-write blocks and write-read blocks, for enhancing the tampering proof characteristics of said flash memory (110), said certificates authenticating a computer program and being verified by a verification program associated with the computer program, said method comprising the steps of: (230) defining a plurality of memory slots within said at least one erased erase-write block wherein each memory slot have a commencing address comprising a binary “0”- or a binary “1” bit pattern, (240) writing a first and second digital certificate in a first and second one of said memory slots, (250) defining a certificate slot address pointer, (260) updating said certificate slot address pointer by replacing said “0”- or “1”-bit pattern of said pointer with a “1”-or a “0” bit pattern, respectively.
    • 本发明一般涉及数据安全和数据存储技术,更具体地说,提供了一种用于在闪速存储器中存储和更新数字证书的方法,还提供了利用所述方法的闪速存储器和电子设备。 根据本发明的方法适用于具有预定义的擦除写入块和写入读取块的闪存(110),用于增强所述闪存(110)的防篡改特性,所述证书认证计算机程序并被验证 通过与所述计算机程序相关联的验证程序,所述方法包括以下步骤:(230)在所述至少一个擦除擦除写入块内定义多个存储器时隙,其中每个存储器时隙具有包含二进制“0”的开始地址, - 或二进制“1”位模式,(240)在第一和第二所述存储器时隙中写入第一和第二数字证书,(250)定义证书时隙地址指针,(260)更新所述证书时隙地址指针 通过用“1”或“0”位模式分别替换所述指针的所述“0”或“1”位模式。