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81. 发明申请

WO2019005113A1 RESISTIVE RANDOM-ACCESS MEMORY INCLUDING TUNNEL SOURCE ACCESS TRANSISTOR 审中-公开
公开(公告)号：WO2019005113A1
公开(公告)日：2019-01-03
申请号：PCT/US2017/040321
申请日：2017-06-30
申请人： INTEL CORPORATION
发明人： MORRIS, Daniel H. , AVCI, Uygar E. , YOUNG, Ian A.
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： H01L27/2436 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0078 , G11C2213/72 , G11C2213/74 , G11C2213/79 , H01L27/2418
摘要： Techniques are disclosed for forming resistive random-access memory (RRAM) including a tunnel source access transistor, such as a tunnel source MOSFET. The use of a tunnel source access transistor includes integrating a tunnel diode on the bitcell transistor's source terminal using epitaxial growth. Accordingly, such RRAM bitcells are referred to herein as having a 1T(D)-1R configuration. As can be understood based on this disclosure, the tunnel diode's resistance is asymmetric with respect to RRAM write voltage. Thus, the tunnel diode optimizes array operations for the 1T(D)-1R bitcells described herein, enabling both control of current compliance in the SET direction and maximization of current in the RESET direction from the same RRAM bitcell. The 1T(D)-1R architecture is compatible with a multitude of RRAM device structures and transistor types, such as NMOS and PMOS configurations. Further, the tunnel diode can be integrated in a MOSFET access transistor without increasing cell layout area.

82. 发明申请

WO2018236366A1 COLOSSAL MAGNETORESISTANCE FOR MAGNETIC READ OUT 审中-公开
公开(公告)号：WO2018236366A1
公开(公告)日：2018-12-27
申请号：PCT/US2017/038472
申请日：2017-06-21
申请人： INTEL CORPORATION , MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
发明人： MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： H01L43/08 , H01L43/02 , H01L43/10
CPC分类号： H01L43/02 , H01L43/08 , H01L43/10
摘要： Embodiments are generally directed to colossal magnetoresistance for magnetic read out utilizing Heusler alloys. An embodiment of a spin logic device includes a magnetic tunnel junction, which includes a stack including a plurality of layers, the stack including a ferromagnetic fixed layer, a ferromagnetic free layer, and a giant magnetoresistance layer between the ferromagnetic fixed layer and the first ferromagnetic free layer.

83. 发明申请

WO2018231210A1 THIN FILM FERROELECTRIC MATERIALS AND METHODS OF FABRICATION THEREOF 审中-公开
公开(公告)号：WO2018231210A1
公开(公告)日：2018-12-20
申请号：PCT/US2017/037352
申请日：2017-06-14
申请人： INTEL CORPORATION
发明人： HOWARD, Joshua M. , KIM, Seiyon , AVCI, Uygar E. , YOUNG, Ian A.
IPC分类号： H01L45/00
CPC分类号： G11C11/223 , G11C11/221 , H01L27/11507 , H01L27/1159 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391
摘要： Described herein are two approaches for providing thin film ferroelectric materials. The first approach is based on using a templating layer in contact with a ferroelectric layer, the material of the templating layer being such that it imparts stress or strain, and/or provides nucleation sites that result in a conversion of the material(s) of the ferroelectric layer to the orthorhombic crystal structure, possibly upon annealing. The second approach is based on including network stabilizing materials within the ferroelectric layer to modify the overall crystallinity and crystalline phases of the layer. Both approaches may improve the orthorhombic crystal structure of the resulting ferroelectric layer, leading to improvements in the ferroelectric behavior of the layer, e.g. in terms of higher remnant polarization, endurance cycles, and retention times. In various embodiments, these approaches may be used in combination, as well as in isolation.

84. 发明申请

WO2018186826A1 OPTICAL TRANSDUCTION FOR MAGNETO-ELECTRIC SPIN ORBIT LOGIC 审中-公开
公开(公告)号：WO2018186826A1
公开(公告)日：2018-10-11
申请号：PCT/US2017/025736
申请日：2017-04-03
申请人： INTEL CORPORATION
发明人： MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： H01L43/02 , H01L31/08 , H01L43/10 , G11C11/16
CPC分类号： G02F3/00 , G11C11/1675 , G11C13/04 , H01L31/08 , H03K19/168 , H03K19/18
摘要： Embodiments are generally directed to optical transduction for Magneto-Electric Spin Orbit (MESO) logic. An embodiment of an apparatus includes an optical waveguide to receive an optical input; and an optical to electrical transducer, the optical to electrical transducer including an optical to charge converter, a charge to magnetic state converter, and a magnetic state to charge converter.

85. 发明申请

WO2018125248A1 HEUSLER ALLOY BASED MAGNETIC TUNNEL JUNCTIONS AND REFRACTORY INTERCONNECTS 审中-公开
公开(公告)号：WO2018125248A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/069638
申请日：2016-12-31
申请人： INTEL CORPORATION , MANIPATRUNI, Sasikanth , CHAWLA, Jasmeet S. , WIEGAND, Christopher J. , NIKONOV, Dmitri E. , GOLONZKA, Oleg , YOUNG, Ian A.
发明人： MANIPATRUNI, Sasikanth , CHAWLA, Jasmeet S. , WIEGAND, Christopher J. , NIKONOV, Dmitri E. , GOLONZKA, Oleg , YOUNG, Ian A.
IPC分类号： H01L43/10 , H01L43/02 , H01L43/08
CPC分类号： H01L43/08 , G11C11/161 , H01F10/1936 , H01F10/3254 , H01F10/3272 , H01L27/222 , H01L43/10
摘要： Embodiments are generally directed to Heusler alloy based magnetic tunnel junctions and refractory interconnects. An embodiment of an apparatus includes a magnetic tunnel junction (MTJ) stack of an MRAM (Magnetoresistive Random Access Memory), the MTJ stack including a free magnetic layer and a fixed magnetic later, wherein the magnetic tunnel junction stack including one or more Heusler alloys; and metal interconnects for the MRAM, wherein the metal interconnects include one or more refractory metals, Silicides or Germinides of Nickel or Cobalt, refractory Heusler alloy, or Silicides of Heusler alloy.

86. 发明申请

WO2018125042A1 SUPER LATTICES FOR MAGNETOELECTRIC AND FERROELECTRIC LOGIC 审中-公开
公开(公告)号：WO2018125042A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/068684
申请日：2016-12-27
申请人： INTEL CORPORATION
发明人： MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： H01L43/02 , H01L43/10 , H01L43/12
CPC分类号： H01L27/226 , H01L43/08 , H01L43/10 , H01L43/12
摘要： An apparatus is provided which comprises: a first magnet with perpendicular magnetic anisotropy (PMA); a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba effect (IRBE); a second magnet with PMA; a multi-layer stack to provide magnetoelectric effect, wherein the multi-layer stack is adjacent to the second magnet; and a conductor coupled to at least a portion of the stack of layers and the multi-layer stack.

87. 发明申请

WO2018118091A1 MAGNETO-ELECTRIC SPIN ORBIT (MESO) STRUCTURES HAVING FUNCTIONAL OXIDE VIAS 审中-公开
公开(公告)号：WO2018118091A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068584
申请日：2016-12-23
申请人： INTEL CORPORATION , CHAWLA, Jasmeet S. , MANIPATRUNI, Sasikanth , BRISTOL, Robert L. , LIN, Chia-Ching , NIKONOV, Dmitri E. , YOUNG, Ian A.
发明人： CHAWLA, Jasmeet S. , MANIPATRUNI, Sasikanth , BRISTOL, Robert L. , LIN, Chia-Ching , NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： H01L43/02 , H01L43/10 , H01L43/12
摘要： Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.

88. 发明申请

WO2018106212A1 QUATERNARY SPIN HALL MEMORY 审中-公开
公开(公告)号：WO2018106212A1
公开(公告)日：2018-06-14
申请号：PCT/US2016/065023
申请日：2016-12-05
申请人： INTEL CORPORATION
发明人： MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： H01L43/02 , H01L43/08 , H01L43/10
摘要： An apparatus is provided which comprises: a first magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; a second magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; and a first layer of spin orbit coupling material adjacent to the first magnetic junction and the second magnetic junction via their respective 4-state free magnetic layers. Described is an apparatus which comprises a 4-state free magnetic layer; a layer of SOC material adjacent to the 4-state free magnetic layer; a first interconnect coupled to the layer of SOC material.

89. 发明申请

WO2018063310A1 TUNNELING TRANSISTORS INCLUDING SOURCE/DRAIN REGIONS EMPLOYING DIFFERENT SEMICONDUCTOR MATERIAL 审中-公开
标题翻译：包括使用不同半导体材料的源/漏区的隧道晶体管
公开(公告)号：WO2018063310A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054724
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , MURTHY, Anand S. , YOUNG, Ian A. , AVCI, Uygar E.
IPC分类号： H01L29/78 , H01L29/73 , H01L29/66 , H01L21/8238 , H01L29/423
CPC分类号： H01L29/7391 , H01L21/823418 , H01L21/823481 , H01L29/0834 , H01L29/165 , H01L29/205 , H01L29/423 , H01L29/66356 , H01L29/775 , H01L29/785
摘要： Techniques are disclosed for forming tunneling transistors including source and drain (S/D) regions employing different material. Using material bandgap engineering, the techniques enhance the ability of transistor devices that employ quantum tunneling, such as tunnel field-effect transistors (TFETs) and Fermi filter FETs (FFFETs), to resist off-state leakage currents from source to drain (through the channel) and from source to ground/substrate. The material bandgap engineering can incorporate a material-based band offset component to control off-state leakage. Such a band offset can expand upon the limited energy band offset achievable using conventional material configurations (e.g., single composition material configurations), because with such conventional material configurations, above a threshold doping concentration, there is no additional decrease in leakage current for a given source to drain voltage at fixed dimensions. For example, increasing the band offset can increase the barrier that carriers must overcome to reach the channel region, thereby reducing off-state leakage.
摘要翻译：公开了用于形成包括采用不同材料的源极和漏极（S / D）区域的隧穿晶体管的技术。利用材料带隙工程技术，这些技术增强了采用量子隧穿技术的晶体管器件（如隧道场效应晶体管（TFET）和费米滤波器FET（FFFET））的能力，可以抵抗从源极到漏极的截止状态泄漏电流（通过通道）以及从源到地/衬底。材料带隙工程可以结合基于材料的带偏移分量来控制关态漏电。这种频带偏移可以在利用常规材料配置（例如，单一组合材料配置）可实现的有限能带偏移时扩大，因为对于给定的给定阈值掺杂浓度以上的这种常规材料配置，不存在额外的漏电流降低源以固定尺寸的漏极电压。例如，增加频带偏移可以增加载波必须克服才能到达信道区域的屏障，从而减少关闭状态泄漏。

90. 发明申请

WO2018004700A1 TRANSISTORS WITH METAL SOURCE AND DRAIN CONTACTS INCLUDING A HEUSLER ALLOY 审中-公开
标题翻译：晶体管与金属源和漏极接触，包括HEUSLER合金
公开(公告)号：WO2018004700A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040877
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： MANIPATRUNI, Sasikanth , ANURAG, Chaudhry , NIKONOV, Dmitri E. , CHAWLA, Jasmeet S. , WIEGAND, Christopher J. , KANWALJIT, Singh , AVCI, Uygar E. , YOUNG, Ian A.
IPC分类号： H01L29/78 , H01L21/8238 , H01L29/66
CPC分类号： H01L29/66984 , B82Y10/00 , H01L21/28537 , H01L21/28581 , H01L29/0669 , H01L29/0673 , H01L29/1054 , H01L29/16 , H01L29/20 , H01L29/24 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/452 , H01L29/456 , H01L29/47 , H01L29/475 , H01L29/66356 , H01L29/66439 , H01L29/66469 , H01L29/7391 , H01L29/775 , H01L29/7849 , H01L29/785 , H01L29/78654 , H01L29/78681
摘要： Embodiments herein describe techniques for a semiconductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.
摘要翻译：这里的实施例描述了用于包括具有第一半导体材料的沟道的半导体器件的技术; 耦合到所述通道的源极触点，包括第一赫斯勒合金; 以及耦合到通道的漏极触点，其包括第二赫斯勒合金。第一赫斯勒合金在第一预定阈值内与第一半导体材料晶格匹配。沟道与源极接触之间的第一肖特基势垒以及沟道与漏极接触之间的第二肖特基势垒是负的或小于另一预定阈值。源极触点和漏极触点可应用于应变硅晶体管，III-V晶体管，隧道场效应晶体管，二硫族化合物（MX2）晶体管和无结纳米线晶体管。

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