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81. 发明授权

US5972753A Method of self-align cell edge implant to reduce leakage current and improve program speed in split-gate flash 失效
标题翻译：自对准单元边缘注入的方法，以减少漏电流并提高分闸门闪存中的编程速度
公开(公告)号：US5972753A
公开(公告)日：1999-10-26
申请号：US984842
申请日：1997-12-04
申请人： Yai-Fen Lin , Hung-Cheng Sung , Chia-Ta Hsieh , Di-Son Kuo
发明人： Yai-Fen Lin , Hung-Cheng Sung , Chia-Ta Hsieh , Di-Son Kuo
IPC分类号： H01L21/336 , H01L29/423 , H01L21/8247
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A method is provided for fabricating a self-aligned edge implanted split-gate flash memory comprising a semiconductor substrate of a first conductivity type having separated first and second regions of a second conductivity type formed therein, the first and second regions defining a substrate channel region therebetween; a floating gate separated from a doped region in the substrate by an oxide layer; a control gate partially overlying and separated by an insulator from said floating gate; said floating gate having thin portions and thick portions; and said thin portions of said floating gate overlying twice doped regions said semiconductor substrate to reduce surface leakage current and improve program speed of the memory cell.
摘要翻译：提供了一种用于制造自对准边缘注入分裂栅极闪存的方法，该闪存包括形成有分离的第二和第二区域的第一导电类型的半导体衬底，第一和第二区域限定衬底沟道区域之间; 通过氧化物层与衬底中的掺杂区域分离的浮置栅极; 由所述浮动栅极部分地由绝缘体覆盖并分离的控制栅极; 所述浮栅具有薄部分和厚部分; 并且所述浮动栅极的所述薄部分覆盖两个掺杂区域的所述半导体衬底，以减少表面泄漏电流并提高存储器单元的编程速度。

82. 发明授权

US5962903A Planarized plug-diode mask ROM structure 失效
标题翻译：平面化插头二极管掩模ROM结构
公开(公告)号：US5962903A
公开(公告)日：1999-10-05
申请号：US730949
申请日：1996-10-16
申请人： Hung-Cheng Sung , Ling Chen
发明人： Hung-Cheng Sung , Ling Chen
IPC分类号： H01L27/102 , H01L29/861 , H01L29/04 , H01L29/41
CPC分类号： H01L27/1021 , Y10S257/926
摘要： A Mask ROM and a method of manufacture of a Mask ROM on a semiconductor substrate comprises formation of a first plurality of conductor lines in a first array. A dielectric layer is formed upon the device with a matrix of openings therein in line with the first array. The openings expose the surface of the first conductor lines. Semiconductor diodes are formed in the matrix of openings in contact with the first conductor lines. A second plurality of conductor lines are formed on the surface of the dielectric layer in a second array of conductor lines orthogonal to the first plurality of conductor lines in the first array. A second plurality of conductor lines is aligned with the matrix and is in contact with the upper ends of the semiconductor diodes.
摘要翻译：掩模ROM和在半导体衬底上制造掩模ROM的方法包括以第一阵列形成第一多条导体线。电介质层在其上具有与第一阵列一致的开口矩阵的器件上形成。开口露出第一导体线的表面。半导体二极管形成在与第一导线接触的开口矩阵中。在与第一阵列中的第一多个导体线正交的导体线的第二阵列中，在电介质层的表面上形成第二多个导体线。第二多个导体线与矩阵对准并且与半导体二极管的上端接触。

83. 发明授权

US5940706A Process for preventing misalignment in split-gate flash memory cell 失效
标题翻译：用于防止分闸式闪存单元中的未对准的过程
公开(公告)号：US5940706A
公开(公告)日：1999-08-17
申请号：US988764
申请日：1997-12-11
申请人： Hung-Cheng Sung , Di-Son Kuo , Yai-Fen Lin , Chia-Ta Hsieh
发明人： Hung-Cheng Sung , Di-Son Kuo , Yai-Fen Lin , Chia-Ta Hsieh
IPC分类号： H01L21/336 , H01L29/423 , H01L21/8247
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A select transistor for flash memory cells is made by the following steps. Over the blanket second dielectric layer, and an oxynitride layer form a channel mask for patterning the drain and floating gate. Etch the oxynitride layer through the mask to form a channel alignment mask down to a silicon nitride layer with a drain region opening and a floating gate opening. Etch the floating gate opening through the second dielectric layer. Form a polyoxide region in the floating gate layer at the bottom of the floating gate opening by reacting the exposed portion of the floating gate layer with a reactant. Form a drain region in the substrate. Etch away the oxynitride layer and the silicon nitride layer. Pattern the floating gate electrode by etching away the floating gate layer except below the polyoxide region. Form an interelectrode dielectric layer and a second gate electrode layer over the drain region and a portion of the polyoxide region. Form a source region in the substrate self-aligned with the polyoxide region.
摘要翻译：用于闪存单元的选择晶体管通过以下步骤进行。在整个第二介电层上，并且氧氮化物层形成用于图案化漏极和浮置栅极的沟道掩模。通过掩模蚀刻氧氮化物层以形成通道对准掩模，直到具有漏极区域开口和浮动开口的氮化硅层。通过第二介电层蚀刻浮动开口。通过使浮栅的暴露部分与反应物反应，在浮动栅极开口底部的浮栅中形成多氧化物区域。在衬底中形成漏区。蚀刻掉氧氮化物层和氮化硅层。通过蚀刻除了多晶氧化物区域之外的浮栅层来对浮栅电极进行图案化。在漏极区域和一部分多氧化物区域上形成电极间电介质层和第二栅电极层。在与氧化物区域自对准的衬底中形成源区。

84. 发明授权

US5879992A Method of fabricating step poly to improve program speed in split gate flash 失效
标题翻译：制造步骤聚合物以提高分流栅闪光中程序速度的方法
公开(公告)号：US5879992A
公开(公告)日：1999-03-09
申请号：US115719
申请日：1998-07-15
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-Ke Yeh , Di-Son Kuo
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-Ke Yeh , Di-Son Kuo
IPC分类号： H01L21/336 , H01L29/423 , H01L21/8427
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.
摘要翻译：提供了一种用于形成分支栅极快闪存储器单元的方法，其具有支撑不同厚度的多晶硅氧化物的台阶聚合物，以改善电池的全部性能。多晶氧化物形成在第一多晶硅层的部分上，该第一多晶硅层又被部分蚀刻以形成邻近聚氧化物下面的浮动栅极的侧壁的台阶。接着在步骤poly上由热的温度氧化物形成间隔物。然后形成间极氧氮化物，并且控制栅极被图案化与浮置栅极与介入的多晶硅氧化物重叠。步进多晶硅和间隔件在控制栅极和浮动栅极之间形成适当的距离，同时保持多晶硅尖端和控制栅极之间的距离不变，使得控制栅极和浮动栅极之间以及浮动栅极和浮动栅极之间的适当耦合实现了衬底，从而改进了具有阶梯聚光的分离栅极闪存的全部性能。

85. 发明授权

US5858840A Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash 失效
标题翻译：通过氮注入形成聚合尖锐尖嘴的方法，以提高分流栅闪光的擦除速度
公开(公告)号：US5858840A
公开(公告)日：1999-01-12
申请号：US995341
申请日：1997-12-22
申请人： Chia-Ta Hsieh , Hung-Cheng Sung , Yai-Fen Lin , Di-Son Kuo
发明人： Chia-Ta Hsieh , Hung-Cheng Sung , Yai-Fen Lin , Di-Son Kuo
IPC分类号： H01L21/336 , H01L29/423 , H01L21/82
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory cell. This is accomplished by implanting nitrogen ions in the first polysilicon layer of the cell and removing them from the area where the floating gate is to be formed. Then, when the polysilicon layer is oxidized to form polyoxide, the floating gate region without the nitrogen ions oxidizes faster than the surrounding area still having the nitrogen ions. Consequently, the bird's beak that is formed at the edges of the polyoxide assumes a sharper shape with smaller size than that is found in prior art. This results in an increase in the erase speed of the memory cell.
摘要翻译：提供了一种用于形成短而尖锐的门鸟喙的方法，以便增加分闸式闪存单元的擦除速度。这是通过将氮离子注入到电池的第一多晶硅层中并将其从要形成浮栅的区域中去除来实现的。然后，当多晶硅层被氧化形成聚氧化物时，没有氮离子的浮栅区域比仍然具有氮离子的周围区域更快地氧化。因此，形成在多氧化物边缘的鸟嘴形状比现有技术中发现的具有更小的形状。这导致存储单元的擦除速度的增加。

86. 发明授权

US5734607A Method of manufacturing self-aligned bit-line and device manufactured therby 失效
标题翻译：制造自对准位线和器件制造方法
公开(公告)号：US5734607A
公开(公告)日：1998-03-31
申请号：US688069
申请日：1996-07-29
申请人： Hung-Cheng Sung , Ling Chen
发明人： Hung-Cheng Sung , Ling Chen
IPC分类号： H01L21/8247 , H01L27/115 , H01L23/58
CPC分类号： H01L27/11521 , H01L27/115
摘要： An integrated circuit EPROM memory device includes devices to which electrical connections are to be made. A tunnel oxide layer on a semiconductor substrate carries an array of gate stacks with sidewalls with trench spaces therebetween comprising wider drain trench spaces and narrower source trench spaces down to the tunnel oxide layer. Gate stacks include a doped polysilicon floating gate over the tunnel oxide layer, a dielectric layer over the floating gate, a polysilicon control gate over the dielectric layer covered by a silicon dioxide dielectric layer and a silicon nitride layer. Source/drain regions lie between the stacks with alternating source regions and drain regions below the trench spaces between the sidewalls. Spacers are adjacent to the sidewalls of the drain trench spaces. Spacer dielectric plugs fill source trench spaces. A blanket dielectric layer overlies the stacks and the spacer dielectric plugs. Bitlines extend across the stacks into contact with the drain regions through the drain trench spaces. The memory devices include a self-aligned bitline structure formed simultaneously with electrical contacts to the drains.
摘要翻译：集成电路EPROM存储器件包括要进行电连接的器件。半导体衬底上的隧道氧化物层带有具有其间沟槽空间的侧壁的栅极堆叠阵列，包括更宽的漏极沟槽空间和较窄的沟槽氧化物层的源极沟槽空间。栅极堆叠包括在隧道氧化物层上的掺杂多晶硅浮置栅极，浮置栅极上的电介质层，在由二氧化硅介电层和氮化硅层覆盖的电介质层上的多晶硅控制栅极。源极/漏极区域位于具有交替的源极区域和在侧壁之间的沟槽间隔之下的漏极区域的堆叠之间。隔板与排水槽空间的侧壁相邻。间隔绝缘塞填充源沟槽空间。叠层介电层覆盖在叠层和间隔电介质塞之间。位线延伸穿过堆叠，通过漏极沟槽空间与漏极区域接触。存储器件包括与对漏极的电触点同时形成的自对准位线结构。

87. 发明申请

US20130307080A1 SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS 有权
标题翻译：具有自对准互连的半导体器件
公开(公告)号：US20130307080A1
公开(公告)日：2013-11-21
申请号：US13472890
申请日：2012-05-16
申请人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
发明人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
IPC分类号： H01L27/088 , H01L21/04
CPC分类号： H01L21/823814 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L29/1083 , H01L29/36 , H01L29/423
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括包括金属氧化物器件的衬底。金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。第一和第二掺杂区掺杂有第一类掺杂剂。第一掺杂区具有与第二掺杂区不同的掺杂浓度。金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。源区和漏区掺杂有第二类掺杂剂。第二种掺杂剂与第一种掺杂剂相反。

88. 发明授权

US07176083B2 High write and erase efficiency embedded flash cell 有权
公开(公告)号：US07176083B2
公开(公告)日：2007-02-13
申请号：US10870774
申请日：2004-06-17
申请人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
发明人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7885
摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

89. 发明申请

US20060203537A1 METHODS AND DEVICES FOR DETERMINING WRITING CURRENT FOR MEMORY CELLS 有权
标题翻译：用于确定记忆细胞的写入电流的方法和装置
公开(公告)号：US20060203537A1
公开(公告)日：2006-09-14
申请号：US11078171
申请日：2005-03-11
申请人： Hung-Cheng Sung , Der-Shin Shyu
发明人： Hung-Cheng Sung , Der-Shin Shyu
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.
摘要翻译：确定存储单元写入电流的方法。将第一参考电流施加到第一操作线以将存储器单元切换到第一状态。第二参考电流被施加到穿过第一操作线的第二操作线，以将存储器单元切换到第二状态。根据第一比率和第一参考电流获得第一写入电流。根据第二比例和第二参考电流获得第二写入电流。通过将第一写入电流施加到第一操作线并将第二写入电流施加到第二操作线来编程存储器单元。

90. 发明申请

US20050282337A1 High write and erase efficiency embedded flash cell 有权
标题翻译：高写入和擦除效率嵌入式闪存单元
公开(公告)号：US20050282337A1
公开(公告)日：2005-12-22
申请号：US10870774
申请日：2004-06-17
申请人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
发明人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
IPC分类号： H01L21/336 , H01L21/4763 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7885
摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.
摘要翻译：一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间的结构中的源极区域，源极植入物并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。还提供了一种形成嵌入式闪存单元结构的方法。

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