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81. 发明申请

US20110227144A1 HIGH-PERFORMANCE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：高性能半导体器件及其制造方法
公开(公告)号：US20110227144A1
公开(公告)日：2011-09-22
申请号：US12999086
申请日：2010-06-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/495 , H01L21/26513 , H01L21/2652 , H01L21/2658 , H01L21/26586 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/66492 , H01L29/66545
摘要： The present invention relates to a method of manufacturing a semiconductor device, and the method uses the mode of thermal annealing the source/drain regions and performing Halo ion implantation to form a Halo ion-implanted region by: first removing the dummy gate to expose the gate dielectric layer to form an opening; then performing a tilted Halo ion implantation to the device from the opening to form a Halo ion-implanted region on both sides of the channel of the semiconductor device; and then annealing to activate the dopants in the Halo ion-implanted region; finally performing subsequent process to the device according to the requirement of the manufacture process. Through the present invention, the dopants in the Halo ion-implanted region improperly introduced to the source region and the drain region may be reduced, and then the overlap between the Halo ion-implantation region and the dopant region of the source/drain regions may be reduced, thus to reduce the band-band leakage current in the MOSFET, and hence improve the performance of the device.
摘要翻译：本发明涉及一种制造半导体器件的方法，该方法使用对源/漏区进行热退火的方式，并进行Halo离子注入以形成Halo离子注入区域，方法是首先去除伪栅极以暴露出栅介电层形成开口; 然后从所述开口对所述器件进行倾斜的Halo离子注入，以在所述半导体器件的沟道的两侧上形成Halo离子注入区域; 然后退火以激活卤素离子注入区域中的掺杂剂; 最后根据制造过程的要求对设备进行后续处理。通过本发明，可以减少不适当地引入源极区域和漏极区域的卤素离子注入区域中的掺杂剂，然后卤素离子注入区域和源极/漏极区域的掺杂剂区域之间的重叠可以减小，从而降低MOSFET中的带带漏电流，从而提高器件的性能。

82. 发明授权

US07897468B1 Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island 有权
标题翻译：具有通过背面工程形成的自对准双门的装置，以及具有超陡峭退化岛的装置
公开(公告)号：US07897468B1
公开(公告)日：2011-03-01
申请号：US12556604
申请日：2009-09-10
申请人： Zhijiong Luo , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/1083 , H01L29/165 , H01L29/66484 , H01L29/6659 , H01L29/66636 , H01L29/66742 , H01L29/7831 , H01L29/78648
摘要： A method of forming a dual gate semiconductor device is provided that includes providing a substrate having a first semiconductor layer and a second semiconductor layer, in which a first gate structure is formed on the second semiconductor layer. The second semiconductor layer and the first semiconductor layer are etched to expose the substrate using the first gate structure as an etch mask. A remaining portion of the first semiconductor layer is present underlying the first gate structure having edges aligned to the edges of the first gate structure. An epitaxial semiconductor material is formed on exposed portions of the substrate. The substrate and the remaining portion of the first semiconductor layer are removed to provide a recess having edges aligned to the edges of the first gate structure, and a second gate structure is formed in the recess. A method of forming a retrograded island is also provided.
摘要翻译：提供一种形成双栅极半导体器件的方法，其包括提供具有第一半导体层和第二半导体层的衬底，其中在第二半导体层上形成第一栅极结构。蚀刻第二半导体层和第一半导体层以使用第一栅极结构作为蚀刻掩模来露出衬底。第一半导体层的剩余部分位于具有与第一栅极结构的边缘对准的边缘的第一栅极结构下方。在衬底的暴露部分上形成外延半导体材料。去除衬底和第一半导体层的剩余部分以提供具有与第一栅极结构的边缘对准的边缘的凹部，并且在凹部中形成第二栅极结构。还提供了形成退火岛的方法。

83. 发明授权

US10096717B2 MOSFET and method for manufacturing the same 有权
公开(公告)号：US10096717B2
公开(公告)日：2018-10-09
申请号：US13510407
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/336 , H01L29/786 , H01L21/265 , H01L29/66 , H01L21/74
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.

84. 发明授权

US09583622B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09583622B2
公开(公告)日：2017-02-28
申请号：US14407263
申请日：2012-07-06
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Qingqing Liang
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Qingqing Liang
IPC分类号： H01L27/12 , H01L29/78 , H01L29/66 , H01L29/732 , H01L29/737 , H01L29/786 , H01L21/02 , H01L21/265 , H01L21/306 , H01L21/324 , H01L21/762 , H01L29/04 , H01L29/06 , H01L29/16 , H01L29/161
CPC分类号： H01L29/7849 , H01L21/0245 , H01L21/02513 , H01L21/265 , H01L21/30604 , H01L21/324 , H01L21/76224 , H01L21/76254 , H01L21/76283 , H01L29/04 , H01L29/0653 , H01L29/16 , H01L29/161 , H01L29/66242 , H01L29/66272 , H01L29/66568 , H01L29/66772 , H01L29/732 , H01L29/7371 , H01L29/78654
摘要： The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench. The semiconductor structure and the method for manufacturing the same disclosed in the present invention provide a favorable stress for the channel of the semiconductor device by introducing a stress layer and a stress induced zone set at specific positions depending on device type to help improving the performance of the semiconductor device.
摘要翻译：本发明公开了一种半导体结构及其制造方法，其特征在于，在基板上设置基板，形成应力层，埋入氧化物层，SOI层，在应力层中形成布置在特定位置的应力层的掺杂区域; 在所述SOI层上形成氧化物层和氮化物层，形成蚀刻所述氮化物层，所述氧化物层，所述SOI层和所述埋入氧化物层的第一沟槽，并停止在所述应力层的上表面上，以及暴露应力层的掺杂区域的至少一部分; 通过所述第一沟槽的湿蚀刻形成空腔以移除所述应力层的掺杂区域; 通过用多晶硅填充空腔并回蚀而形成应力层的多晶硅区域和第二沟槽; 通过填充第二沟槽形成隔离区域。在本发明中公开的半导体结构及其制造方法通过根据器件类型在特定位置引入应力层和应力诱导区域来为半导体器件的沟道提供有利的应力，以有助于提高半导体器件。

85. 发明授权

US09548317B2 FDSOI semiconductor structure and method for manufacturing the same 有权
标题翻译： FDSOI半导体结构及其制造方法
公开(公告)号：US09548317B2
公开(公告)日：2017-01-17
申请号：US14397586
申请日：2012-05-22
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/84 , H01L27/12 , H01L29/66 , H01L29/786 , H01L21/02 , H01L21/266 , H01L21/306 , H01L21/308 , H01L21/768 , H01L29/78 , H01L21/74 , H01L21/265 , H01L29/165
CPC分类号： H01L27/1203 , H01L21/02529 , H01L21/02532 , H01L21/2652 , H01L21/266 , H01L21/30604 , H01L21/3081 , H01L21/743 , H01L21/76897 , H01L21/84 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/78 , H01L29/78612 , H01L29/78648
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes formation of a buried ground layer contact plug, which then connects buried ground layer electrically to source region, thereby enhancing control capabilities of a semiconductor device over threshold voltages, suppressing short-channel effects and improving device performance; whereas no independent contact is required to build for the buried ground layer, which then saves device area and simplifies manufacturing process accordingly.
摘要翻译：本发明提供了一种制造半导体结构的方法，其包括以下步骤：提供基底，其基本层向上依次包括掩埋隔离层，埋地层，超薄绝缘掩埋层和表面活性层对埋地层进行离子注入掺杂; 在衬底上形成栅极堆叠，侧壁间隔物和源极/漏极区域; 在覆盖栅极堆叠和源极/漏极区域的衬底上形成掩模层，并蚀刻掩模层以暴露源极区域; 蚀刻源极区域下的源极区域和超薄绝缘掩埋层，形成暴露埋入地层的开口; 通过外延工艺填充开口以形成埋地层的接触塞。因此，本发明还提供一种半导体结构。本发明提出了一种掩埋地层接触塞的形成，其然后将掩埋地层电连接到源极区，从而提高半导体器件在阈值电压上的控制能力，抑制短沟道效应并提高器件性能; 而不需要独立的接触来构建埋地层，从而节省设备面积并相应地简化制造过程。

86. 发明授权

US09087691B2 Method for manufacturing graphene nano-ribbon, mosfet and method for manufacturing the same 有权
标题翻译：石墨烯纳米带的制造方法，其制造方法及其制造方法
公开(公告)号：US09087691B2
公开(公告)日：2015-07-21
申请号：US13510390
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/20 , H01L21/36 , H01L21/02 , H01L29/775 , H01L29/06 , H01L29/16 , H01L29/20 , H01L29/66 , H01L29/786 , B82Y10/00 , B82Y40/00 , B82Y30/00
CPC分类号： H01L21/0242 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/02422 , H01L21/02488 , H01L21/02491 , H01L21/02507 , H01L21/02527 , H01L21/02639 , H01L29/0673 , H01L29/1606 , H01L29/2003 , H01L29/66742 , H01L29/775 , H01L29/78684 , H01L29/78696
摘要： A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.
摘要翻译：提供了具有石墨烯纳米带的MOSFET及其制造方法。 MOSFET包括绝缘基板; 和绝缘基板上的氧化物保护层。至少一个石墨烯纳米带被嵌入在氧化物保护层中并且具有暴露在氧化物保护层的侧表面的表面。在所述至少一个石墨烯纳米带的每个中设置有沟道区。在所述至少一个石墨烯纳米带的每一个中设置源极区和漏极区。沟道区位于源区和漏区之间。栅电介质位于至少一个石墨烯纳米带上。栅极电介质上的栅极导体。源极和漏极触点分别在氧化物保护层的侧表面上接触源极区域和漏极区域。

87. 发明授权

US09018739B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09018739B2
公开(公告)日：2015-04-28
申请号：US13060468
申请日：2010-09-25
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/04 , H01L29/78 , H01L29/10 , H01L29/165 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/7834 , H01L29/045 , H01L29/105 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/66651
摘要： The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; a second semiconductor layer surrounding the first semiconductor layer; a high k dielectric layer and a gate conductor formed on the first semiconductor layer; source/drain regions formed in the second semiconductor layer, wherein the second semiconductor layer has a slant sidewall in contact with the first semiconductor layer. The semiconductor device has an increased output current, an increased operating speed, and a reduced power consumption due to the channel region of high mobility.
摘要翻译：本申请公开了一种半导体器件及其制造方法。半导体器件包括半导体衬底; 半导体衬底上的第一半导体层; 围绕所述第一半导体层的第二半导体层; 形成在第一半导体层上的高k电介质层和栅极导体; 形成在第二半导体层中的源/漏区，其中第二半导体层具有与第一半导体层接触的倾斜侧壁。半导体器件具有增加的输出电流，增加的操作速度以及由于高移动性的沟道区域而导致的功率消耗降低。

88. 发明授权

US09012274B2 Method of manufacturing a semiconductor fin using sacrificial layer 有权
标题翻译：使用牺牲层制造半导体翅片的方法
公开(公告)号：US09012274B2
公开(公告)日：2015-04-21
申请号：US13580965
申请日：2012-05-14
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/84 , H01L21/20 , H01L27/12 , H01L29/06 , H01L29/66
CPC分类号： H01L21/20 , H01L27/1211 , H01L29/0657 , H01L29/66795
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming an insulating film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin. Correspondingly, the present invention further provides a semiconductor structure. In the present invention, an oxide film is formed on the sidewalls of the two semiconductor fins that are far away from each other, while only the sidewalls of the two semiconductor fins that are opposite to each other are exposed, such that conventional operations may be easily performed to the sidewalls opposite to each other in the subsequent process.
摘要翻译：本发明提供一种制造半导体结构的方法，包括以下步骤：提供半导体衬底，在半导体衬底上形成绝缘层，并在绝缘层上形成半导体基底层; 在所述半导体基底层上形成包围所述牺牲层的牺牲层和间隔物，并且通过以所述间隔物作为掩模来蚀刻所述半导体基底层以形成半导体本体; 在半导体主体的侧壁上形成绝缘膜; 去除位于牺牲层下方的牺牲层和半导体本体以形成第一半导体鳍片和第二半导体鳍片。相应地，本发明还提供一种半导体结构。在本发明中，在远离彼此的两个半导体翅片的侧壁上形成氧化膜，只有两个相互相对的两个半导体翅片的侧壁露出，这样常规的操作可以是在随后的过程中容易地对彼此相对的侧壁进行。

89. 发明申请

US20140362652A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ACCESSING THE SAME 有权
标题翻译：半导体存储器件及其接收方法
公开(公告)号：US20140362652A1
公开(公告)日：2014-12-11
申请号：US14355120
申请日：2012-03-22
申请人： Zhijiong Luo , Zhengyong Zhu , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Zhengyong Zhu , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/105 , H01L29/267 , G11C7/00 , H01L29/786
CPC分类号： H01L27/1052 , G11C5/06 , G11C7/00 , G11C8/16 , G11C11/404 , G11C11/405 , H01L27/108 , H01L29/267 , H01L29/7869
摘要： A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.
摘要翻译：公开了一种半导体存储器件及其访问方法。半导体存储器件包括存储晶体管，第一控制晶体管和第二控制晶体管，其中第一控制晶体管的源电极和栅电极分别耦合到第一位线和第一字线，漏电极和第二控制晶体管的栅电极分别耦合到第二字线和第二位线，存储晶体管的栅电极耦合到第一控制晶体管的漏电极，存储晶体管的漏电极耦合到第二控制晶体管的源电极，并且存储晶体管的源电极耦合到地，并且其中存储晶体管表现出栅电极控制的存储特性。半导体存储器件增加了集成度并降低了刷新频率。

90. 发明授权

US08889554B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08889554B2
公开(公告)日：2014-11-18
申请号：US13380486
申请日：2011-04-18
申请人： Haizhou Yin , Wei Jiang , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Wei Jiang , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/78 , H01L29/417 , H01L29/66
CPC分类号： H01L29/41775 , H01L29/456 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure. The present invention is beneficial to the suppression of the diffusion of corresponding compositions from the contact layers into the channel region, reduction of the short channel effects, and improvement of the reliability of the semiconductor structure.
摘要翻译：本发明提供一种制造半导体结构的方法，包括：在第一间隔物的暴露的有源区上形成第一接触层; 在所述第一接触层的靠近栅极堆叠的区域处形成第二间隔物以部分地覆盖所述暴露的有源区; 在未覆盖的暴露的有源区中形成第二接触层，其中当第一接触层的扩散系数与第二接触层的扩散系数相同时，第一接触层的厚度小于第二接触层的厚度; 并且当第一接触层的扩散系数与第二接触层的扩散系数不同时，第一接触层的扩散系数小于第二接触层的扩散系数。相应地，本发明还提供一种半导体结构。本发明有利于抑制相应组合物从接触层扩散到沟道区中，减少短沟道效应，提高半导体结构的可靠性。

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