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81. 发明授权

US06255215B1 Semiconductor device having silicide layers formed using a collimated metal layer 有权
标题翻译：具有使用准直金属层形成的硅化物层的半导体器件
公开(公告)号：US06255215B1
公开(公告)日：2001-07-03
申请号：US09175652
申请日：1998-10-20
申请人： Fred Hause , Charles E. May , William S. Brennan
发明人： Fred Hause , Charles E. May , William S. Brennan
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： A process for forming a silicide layer using a metal layer formed by collimated deposition is provided. The collimated metal layer may, for example, be formed by sputtering metal particles and filtering the metal particles prior to forming the metal layer. By depositing metal in this manner, the resistance of the resultant metal silicide layer can be reduced as compared to metal silicide layers formed using conventional techniques. Lower silicidation reaction temperatures may also be employed.
摘要翻译：提供了使用通过准直沉积形成的金属层形成硅化物层的工艺。准直金属层可以例如通过溅射金属颗粒并在形成金属层之前过滤金属颗粒来形成。通过以这种方式沉积金属，与使用常规技术形成的金属硅化物层相比，所得金属硅化物层的电阻可以降低。也可以采用较低的硅化反应温度。

82. 发明授权

US06194768B1 High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure 失效
标题翻译：高介电常数栅极电介质，其上覆盖的钽栅极导体形成在牺牲结构的侧壁表面上
公开(公告)号：US06194768B1
公开(公告)日：2001-02-27
申请号：US09177867
申请日：1998-10-23
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L31119
CPC分类号： H01L29/518 , H01L21/28114 , H01L21/2815 , H01L21/823418 , H01L21/823437 , H01L29/495 , H01L29/66659
摘要： A transistor is provided having a gate conductor produced with ultra fine geometries. The gate conductor is metallic and is sized using deposition rather than photolithography. The deposition process can be closely controlled to achieve gate lengths less than a few tenths of a micron. The metallic gate conductor serves to source metal atoms during anneal of lightly doped drain regions. The metal atoms migrate to the gate dielectric directly beneath the gate conductor to convert the gate dielectric to a high K dielectric. The high K dielectric is substantially resistant to breakdown yet enjoys the benefits of high speed operation and low threshold turn-on.
摘要翻译：提供具有以超细几何形状制造的栅极导体的晶体管。栅极导体是金属的，其尺寸使用沉积而不是光刻。可以严格控制沉积过程以实现小于十分之几微米的栅极长度。金属栅极导体用于在轻掺杂漏极区退火期间引发金属原子。金属原子迁移到栅极导体正下方的栅极电介质，将栅极电介质转换成高K电介质。高K电介质基本上不会破坏，而且具有高速运行和低阈值开启的优点。

83. 发明授权

US6160300A Multi-layer gate conductor having a diffusion barrier in the bottom layer 有权
标题翻译：在底层中具有扩散阻挡层的多层栅极导体
公开(公告)号：US6160300A
公开(公告)日：2000-12-12
申请号：US238081
申请日：1999-01-26
申请人： Mark I. Gardner , Derick J. Wristers , Charles E. May
发明人： Mark I. Gardner , Derick J. Wristers , Charles E. May
IPC分类号： H01L21/28 , H01L21/321 , H01L21/336 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28035 , H01L21/321 , H01L29/4925 , H01L29/6659
摘要： A fabrication process and transistor are described in which a transistor having a diffusion barrier located in the bottom layer of a stacked (i.e., multi-layer) gate conductor is formed, thereby reducing the diffusion of dopants from the gate conductor to the underlying channel region. In a general embodiment, multiple gate conductor layers are formed and arranged in a vertical stack, and a diffusion barrier is introduced into one or more layers of the stack. In a preferred dual-layer embodiment, a first gate conductor layer (i.e., the bottom layer) having a first thickness is deposited upon a gate dielectric layer. An argon distribution is then introduced into the first gate conductor layer to form an argon diffusion barrier in the first gate conductor layer. A second gate conductor layer having a second thickness is then deposited upon the first gate conductor layer. The second thickness is preferably greater than the first thickness, which in turn is greater than the thickness of the argon diffusion barrier residing within the first gate conductors layer. The thickness of the first gate conductor layer is controlled to facilitate location of the diffusion barrier, thereby presenting numerous advantages over conventional barrier formation techniques.
摘要翻译：描述了一种制造工艺和晶体管，其中形成具有位于层叠（即，多层）栅极导体的底层中的扩散阻挡层的晶体管，从而减少掺杂剂从栅极导体到底层沟道区域的扩散。在一般实施例中，多个栅极导体层形成并布置成垂直堆叠，并且扩散阻挡层被引入堆叠的一个或多个层中。在优选的双层实施例中，具有第一厚度的第一栅极导体层（即，底层）沉积在栅极介电层上。然后将氩分布引入到第一栅极导体层中，以在第一栅极导体层中形成氩扩散阻挡层。然后将具有第二厚度的第二栅极导体层沉积在第一栅极导体层上。第二厚度优选地大于第一厚度，其又大于驻留在第一栅极导体层内的氩扩散阻挡层的厚度。控制第一栅极导体层的厚度以便于扩散阻挡层的定位，从而与常规屏障形成技术相比具有许多优点。

84. 发明授权

US6156649A Method of forming uniform sheet resistivity salicide 失效
标题翻译：形成均匀的电阻率自对准硅胶的方法
公开(公告)号：US6156649A
公开(公告)日：2000-12-05
申请号：US60434
申请日：1998-04-14
申请人： Fred N. Hause , Robert Dawson , Charles E. May
发明人： Fred N. Hause , Robert Dawson , Charles E. May
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： A semiconductor process in which a first silicide is formed on silicon upper surfaces upon which a second silicide is selectively deposited. A refractory metal is blanket deposited on a semiconductor substrate. The semiconductor substrate is then heated to a first temperature to react portions of the refractory metal above the exposed silicon surfaces to form a first phase of a first silicide. The unreacted portions of the refractory metal then remove, typically with a wet etch process. The semiconductor substrate is then heated to a second temperature to form a second phase of the first silicide. The second temperature is typically greater than the first, and the resistivity of the second phase is less than a resistivity of the first phase. Thereafter, a second metal silicide is selectively deposited on the first silicide, preferably through the use of a chemical vapor deposition process. In one embodiment, the selectively deposited second silicide is reacted with the existing first silicide to form a composite silicide structure exhibiting uniform sheet resistivity independent of the dimensions of the underlying silicon structure.
摘要翻译：一种半导体工艺，其中第一硅化物形成在硅上表面上，在其上选择性地沉积第二硅化物。难熔金属被覆盖在半导体衬底上。然后将半导体衬底加热至第一温度，以使暴露的硅表面上方的难熔金属的部分反应，以形成第一硅化物的第一相。难熔金属的未反应部分通常用湿蚀刻工艺除去。然后将半导体衬底加热至第二温度以形成第一硅化物的第二相。第二温度通常大于第一温度，第二相的电阻率小于第一相的电阻率。此后，优选通过使用化学气相沉积工艺，在第一硅化物上选择性地沉积第二金属硅化物。在一个实施例中，选择性沉积的第二硅化物与现有的第一硅化物反应以形成独立于下面的硅结构的尺寸的均匀的薄层电阻的复合硅化物结构。

85. 发明授权

US6150222A Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions 有权
标题翻译：制造具有升高的间隔物形成和自对准沟道区的高性能晶体管的方法
公开(公告)号：US6150222A
公开(公告)日：2000-11-21
申请号：US226231
申请日：1999-01-07
申请人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
发明人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66757 , H01L29/78636
摘要： The present invention is directed to a transistor formed above a layer of a dielectric material and a method of making same. In one illustrative embodiment, the method comprises forming a first layer of dielectric material, forming a plurality of source/drain regions comprised of polysilicon above said first layer of dielectric material and between said source/drain regions, and forming a second layer of dielectric material above said first layer of dielectric material. The method further comprises forming a layer of polysilicon above the second layer of dielectric material, forming a gate dielectric above said layer of polysilicon, and forming a gate conductor above said gate dielectric. The transistor structure is comprised of a first layer of dielectric material, a plurality of source/drain regions positioned above the first layer of dielectric material, a second layer of dielectric material positioned above the first layer of dielectric material, and a layer of polysilicon positioned above the second layer of dielectric material and between said source/drain regions. The structure further comprises a gate dielectric positioned above the layer of polysilicon and a gate conductor positioned above the gate dielectric.
摘要翻译：本发明涉及一种形成在电介质材料层上方的晶体管及其制造方法。在一个说明性实施例中，该方法包括形成介电材料的第一层，在所述第一介电材料层之上和所述源极/漏极区之间形成由多晶硅构成的多个源/漏区，并形成第二介电材料层在所述第一介电材料层之上。该方法还包括在第二介电材料层之上形成多晶硅层，在所述多晶硅层上形成栅极电介质，并在所述栅极电介质上方形成栅极导体。晶体管结构包括第一介电材料层，位于第一介电材料层之上的多个源极/漏极区域，位于第一介电材料层之上的第二介电材料层和位于在第二介电材料层之上和在所述源/漏区之间。该结构还包括位于多晶硅层之上的栅极电介质和位于栅极电介质上方的栅极导体。

86. 发明授权

US6146983A Method of making semiconductor device having sacrificial salicidation layer 有权
标题翻译：制造具有牺牲性磺化层的半导体器件的方法
公开(公告)号：US6146983A
公开(公告)日：2000-11-14
申请号：US193619
申请日：1998-11-17
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L21/2652
摘要： The present invention is directed to a transistor having a stacked silicide metal and method of making same. In general, the method comprises forming a layer of nitrogen-bearing silicon dioxide above the gate conductor and the source and drain regions of a transistor. In one illustrative embodiment, the method further comprises forming a layer of titanium above at least the surface of the gate conductor and the source and drain regions. Thereafter, a layer of cobalt is formed above the layer of titanium. The transistor is then subjected to a heat treating process such that at least the layer of cobalt forms a metal silicide. Also disclosed herein is a partially formed transistor comprised of a gate conductor, a source region and a gate region. In one illustrative embodiment, the transistor is further comprised of a layer of nitrogen-bearing silicon dioxide formed above the gate conductor and the source and drain regions. The transistor further comprises a layer of titanium positioned adjacent the layer of nitrogen-bearing silicon dioxide and a layer of cobalt positioned adjacent the layer of titanium.
摘要翻译：本发明涉及具有叠层硅化物金属的晶体管及其制造方法。通常，该方法包括在栅极导体和晶体管的源极和漏极区域之上形成含氮二氧化硅层。在一个说明性实施例中，该方法还包括在至少栅极导体的表面和源极和漏极区域的上方形成钛层。此后，在钛层上形成一层钴。然后对晶体管进行热处理工艺，使得至少该钴层形成金属硅化物。本文还公开了由栅极导体，源极区和栅极区组成的部分形成的晶体管。在一个说明性实施例中，晶体管还包括形成在栅极导体和源极和漏极区之上的含氮二氧化硅层。晶体管还包括邻近含氮二氧化硅层定位的钛层和邻近钛层定位的钴层。

87. 发明授权

US6117739A Semiconductor device with layered doped regions and methods of manufacture 有权
标题翻译：具有分层掺杂区域的半导体器件和制造方法
公开(公告)号：US6117739A
公开(公告)日：2000-09-12
申请号：US166000
申请日：1998-10-02
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/266 , H01L21/336 , H01L29/10 , H01L29/49
CPC分类号： H01L29/66583 , H01L21/266 , H01L29/1083 , H01L29/4966 , H01L29/66537
摘要： A semiconductor device can be formed with active regions disposed in a substrate adjacent to a gate electrode and a doped region, of the same conductivity type as the active regions, embedded beneath the channel region defined by the active regions. In one embodiment, a patterned masking layer having at least one opening is formed over the substrate. A dopant material is implanted into the substrate using the masking layer to form active regions adjacent to the opening and an embedded doped region that is between and spaced apart from the active regions and is deeper in the substrate then the active regions. In addition or alternatively, spacer structures can be formed on the gate electrode by forming a conformal dielectric layer along a bottom surface and at least one sidewall of the opening and forming a gate electrode in the opening over the dielectric layer. The masking layer is then removed to leave the dielectric layer between the gate electrode and the substrate and as spacer structures on the sidewalls of the gate electrode.
摘要翻译：可以形成半导体器件，该有源区域设置在与由栅极电极相邻的衬底中的有源区域和与有源区域相同的导电类型的掺杂区域，嵌入在由有源区域限定的沟道区域的下面。在一个实施例中，在衬底上形成具有至少一个开口的图案化掩模层。使用掩模层将掺杂剂材料注入到衬底中以形成与开口相邻的有源区和位于有源区之间并且与有源区间隔开的嵌入的掺杂区，并且在衬底中更深的是有源区。另外或替代地，可以通过沿着底表面和开口的至少一个侧壁形成保形电介质层并在电介质层上的开口中形成栅电极，在栅电极上形成间隔结构。然后去除掩模层以在栅电极和衬底之间留下介电层，并且作为栅电极的侧壁上的间隔结构。

88. 发明授权

US6030875A Method for making semiconductor device having nitrogen-rich active region-channel interface 失效
标题翻译：制造具有富氮有源区 - 沟道界面的半导体器件的方法
公开(公告)号：US6030875A
公开(公告)日：2000-02-29
申请号：US994182
申请日：1997-12-19
申请人： Charles E. May , Robert Dawson , Michael Duane
发明人： Charles E. May , Robert Dawson , Michael Duane
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/167 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L29/7833 , H01L29/167
摘要： A semiconductor device having a nitrogen-rich active region-channel interface and process for fabrication thereof is provided. The nitrogen-rich interface can, for example, can reduce the electric field potential in this region and reduce hot carrier injection effects. Consistent with one embodiment of the invention, a semiconductor device is provided having a substrate, at least one gate electrode disposed over the substrate and an active region disposed adjacent to gate electrode. The semiconductor device further includes a channel region extending from the active region beneath the gate electrode and a nitrogen-rich region disposed at an interface between the channel region and the active region. The nitrogen-rich region may, for example, be disposed at least in part in the channel region. The nitrogen-rich region may, for example, also be disposed at least part of the active region. Further, the active region may be disposed, for example, within the nitrogen-rich region.
摘要翻译：提供了具有富氮有源区 - 沟道界面的半导体器件及其制造方法。例如，富氮界面可以降低该区域的电场电位并减少热载流子注入效应。根据本发明的一个实施例，提供一种半导体器件，其具有衬底，设置在衬底上的至少一个栅电极和邻近栅电极设置的有源区。半导体器件还包括从栅电极下方的有源区延伸的沟道区和设置在沟道区与有源区之间的界面处的富氮区。例如，富氮区域可以至少部分地设置在沟道区域中。例如，富氮区也可以设置在有源区的至少一部分上。此外，有源区可以例如设置在富氮区域内。

89. 发明授权

US5950106A Method of patterning a metal substrate using spin-on glass as a hard mask 失效
标题翻译：使用旋涂玻璃作为硬掩模来图案化金属基板的方法
公开(公告)号：US5950106A
公开(公告)日：1999-09-07
申请号：US647510
申请日：1996-05-14
申请人： Charles E. May , Robert Dawson
发明人： Charles E. May , Robert Dawson
IPC分类号： G03F7/09 , H01L21/033 , H01L21/3213 , H01L21/44
CPC分类号： H01L21/0331 , G03F7/09 , H01L21/32139
摘要： A method for patterning an underlying metal substrate includes forming a layer of spin-on glass over the metal substrate, forming a layer of photoresist over the spin-on glass, patterning the photoresist, patterning the spin-on glass using the photoresist as a mask, and patterning the metal substrate by applying an etch using the spin-on glass as a hard mask wherein the etch removes the photoresist and partially removes the spin-on glass. In one embodiment, the spin-on glass is patterned by applying a fluorine-based plasma, an aluminum-based metal substrate is patterned by applying a chlorine-based plasma in which an etch selectivity of the metal substrate to the spin-on glass is at least 10:1, and the spin-on glass is removed by applying another fluorine-based plasma.
摘要翻译：用于图案化下面的金属衬底的方法包括在金属衬底上形成旋涂玻璃层，在旋涂玻璃上形成光致抗蚀剂层，图案化光致抗蚀剂，使用光致抗蚀剂作为掩模来图案化旋涂玻璃并且通过使用旋涂玻璃作为硬掩模施加蚀刻来对金属基板进行图案化，其中蚀刻去除光致抗蚀剂并部分去除旋涂玻璃。在一个实施例中，通过施加氟基等离子体来对旋涂玻璃进行图案化，通过施加氯基等离子体对铝基金属基板进行图案化，其中金属基板对旋涂玻璃的蚀刻选择性为至少10：1，通过施加另一种氟基等离子体去除旋涂玻璃。

90. 发明授权

US5912493A Enhanced oxidation for spacer formation integrated with LDD implantation 失效
标题翻译：与LDD植入相结合的间隔物形成的增强氧化
公开(公告)号：US5912493A
公开(公告)日：1999-06-15
申请号：US970263
申请日：1997-11-14
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/336 , H01L29/08 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66575 , H01L29/0847 , H01L29/107
摘要： A method for forming a semiconductor device to produce graded doping in the source region and the drain region includes the steps of forming a gate on the surface of the substrate separated from the substrate by a gate oxide, and applying a first ion implantation to implant lightly doped source and drain regions into the substrate, and implanting a material to a portion of the gate oxide over the source region and a portion of the gate oxide over the drain region to vary the rate of oxide formation. An oxide layer is then formed. The resulting oxide layer has at least two thicknesses. Another ion implantation is applied through the formed oxide layer. The ion implantation converts a portion of the lightly doped source region into a heavily doped source region, and converts a portion of the lightly doped drain region into a heavily doped drain region. The implanted ions travel a set distance through the oxide layer formed and into the substrate and more specifically into the source and drain regions formed in the substrate. Therefore, the geometry of the interface between the lightly doped region and the heavily doped region in the source region and the drain region depends on the geometry (thickness and pattern) of oxide layer formed. A set of spacers can also be added after lightly doping the substrate to form the Ldd source and Ldd drain. The geometry of the spacers will also then effect the geometry of the interface between the lightly doped and heavily doped regions within the source and the drain. Also disclosed is a device made by this process as well as an information handling system including such a device.
摘要翻译：一种形成半导体器件以在源极区域和漏极区域中产生渐变掺杂的方法包括以下步骤：通过栅极氧化物在衬底的表面上形成栅极，并施加第一离子注入以轻微地注入掺杂的源极和漏极区域进入衬底，并且将材料注入源极区域上的栅极氧化物的一部分和在漏极区域上的栅极氧化物的一部分以改变氧化物形成速率。然后形成氧化物层。所得到的氧化物层具有至少两个厚度。通过形成的氧化物层施加另一离子注入。离子注入将轻掺杂源区的一部分转换为重掺杂源区，并将轻掺杂漏区的一部分转换为重掺杂漏极区。注入的离子通过形成的氧化物层进入设置的距离，并进一步具体地进入形成在衬底中的源区和漏区。因此，源极区域和漏极区域中的轻掺杂区域和重掺杂区域之间的界面的几何形状取决于形成的氧化物层的几何形状（厚度和图案）。在轻掺杂衬底以形成Ldd源和Ldd漏极之后，也可以添加一组间隔物。间隔物的几何形状还将影响源极和漏极之间的轻掺杂区域和重掺杂区域之间的界面的几何形状。还公开了通过该方法制造的装置以及包括这种装置的信息处理系统。

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