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81. 发明授权

US5257271A Sample data transmission apparatus 失效
标题翻译：样品数据传输装置
公开(公告)号：US5257271A
公开(公告)日：1993-10-26
申请号：US939406
申请日：1992-09-01
申请人： Roger Lagadec , Keisuke Sekiguchi , Hiroyuki Yamauchi , Masaru Tezuka , Satoru Tobita , Yoichiro Sako , Hiroyuki Hara, deceased
发明人： Roger Lagadec , Keisuke Sekiguchi , Hiroyuki Yamauchi , Masaru Tezuka , Satoru Tobita , Yoichiro Sako , Hiroyuki Hara, deceased
IPC分类号： G11B20/18 , H03M13/27 , H04L1/14
CPC分类号： H03M13/2764 , G11B20/1809
摘要： In a sampled data transmitting apparatus in which the sampled data to be transmitted are divided into odd-numbered samples and even-numbered samples and arranged in different rows of a two-dimensional data array, and in which error correction codes are annexed to each row and to each column of the two-dimensional data array, the row arraying sequence in one of the odd-numbered or even-numbered rows is caused to differ from the row arraying sequence in the other of the odd-numbered or even-numbered rows so that odd-numbered data and even-numbered data continuous with the odd-numbered data are not arranged in one row. In this manner, even when error correction becomes impossible by the error correcting code for one row, interpolation remains feasible because there exist no odd-numbered data or even-numbered data contiguous to each other in the row.
摘要翻译：在采样数据发送装置中，将要发送的采样数据划分为奇数样本和偶数样本，并排列在二维数据阵列的不同行中，其中纠错码附于每行并且对于二维数据阵列的每列，使奇数或偶数行之一中的行排列顺序与奇数行或偶数行中的另一行中的行排列顺序不同使得与奇数数据连续的奇数数据和偶数数据不排列在一行中。以这种方式，即使通过一行的纠错码不可能进行纠错，因为在该行中不存在彼此邻接的奇数数据或偶数数据，因此内插仍然是可行的。

82. 发明授权

US5229964A Read circuit for large-scale dynamic random access memory 失效
标题翻译：读取大规模动态随机存取存储器的电路
公开(公告)号：US5229964A
公开(公告)日：1993-07-20
申请号：US617873
申请日：1990-11-26
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C11/413 , C21C5/40 , G11C11/407 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/419 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C11/4096 , G11C11/4091
摘要： A circuit for reading and writing data to/from memory cells of a DRAM, based upon sense amplifiers formed of N-type and P-type FETs for each pair of bit lines of the DRAM and column switches formed of FETs for transferring data potentials to/from the bit line pairs, in which the current drive capability of the column switches is increased relative to the sense amplifiers during each write cycle and the current drive capability of the sense amplifiers is increased relative to that of the column switches during each read cycle, thereby ensuring satisfactory read and write operation even for a very large-scale DRAM operating with a low value of supply voltage.
摘要翻译：基于用于DRAM的每对位线的N型和P型FET形成的读出放大器和用于将数据电位传送到FET的由FET形成的列开关的用于从DRAM的存储单元读取/写入数据的电路来自位线对，其中列开关的当前驱动能力在每个写周期期间相对于读出放大器增加，并且读出放大器的当前驱动能力相对于每个读周期中的列开关的驱动能力增加，从而即使对于具有低电源电压的非常大规模的DRAM进行操作，也能确保令人满意的读写操作。

83. 发明授权

US5051957A Sense amplifier circuit for large-capacity semiconductor memory 失效
标题翻译：用于大容量半导体存储器的感应放大器电路
公开(公告)号：US5051957A
公开(公告)日：1991-09-24
申请号：US462538
申请日：1990-01-03
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C7/065
摘要： A sense amplifier circuit for a semiconductor memory includes a flip-flop coupled to a pair of bit lines connected to memory cells, for amplifying a differential read voltage produced between the bit lines, and at least two switches for applying respectively different levels of drive voltage to a common node of the flip-flop. The switches are controlled such as to apply a relatively high value of drive voltage to the common node when a read operation is initiated, to thereby initially provide a high charging current to the bit line capacitance, and thereafter supply a lower value of drive voltage to thereby ensure reliability of the memory cell oxide film.
摘要翻译：用于半导体存储器的读出放大器电路包括耦合到连接到存储器单元的一对位线的触发器，用于放大在位线之间产生的差分读取电压，以及至少两个开关，分别施加不同级别的驱动电压到触发器的公共节点。控制这些开关，以便在开始读取操作时向公共节点施加相对较高的驱动电压值，从而首先向位线电容提供高充电电流，然后将较低的驱动电压值提供给从而确保记忆单元氧化膜的可靠性。

84. 发明授权

US4920517A Semiconductor memory device having sub bit lines 失效
标题翻译：具有子位线的半导体存储器件
公开(公告)号：US4920517A
公开(公告)日：1990-04-24
申请号：US182895
申请日：1988-04-18
申请人： Hiroyuki Yamauchi , Toshio Yamada , Michihiro Inoue
发明人： Hiroyuki Yamauchi , Toshio Yamada , Michihiro Inoue
IPC分类号： G11C11/4097
CPC分类号： G11C11/4097
摘要： A dynamic random access memory which includes a memory cell array, sense amplifiers disposed at both side of the memory cell array, and sub bit lines coupled to the sense amplifiers. The sub bit lines are coupled to data busses through middle amplifiers. By use of such memory architecture, higher integration of DRAM can be realized. Also, handling of super large bit data more than 1024 bit becomes possible.
摘要翻译：一种动态随机存取存储器，其包括存储单元阵列，设置在存储单元阵列两侧的读出放大器以及耦合到读出放大器的子位线。子位线通过中间放大器耦合到数据总线。通过使用这种存储器架构，可以实现DRAM的更高集成度。而且，超大于1024位的超大位数据的处理成为可能。

85. 发明授权

US4904888A Sense amplifier circuit 失效
标题翻译：感应放大电路
公开(公告)号：US4904888A
公开(公告)日：1990-02-27
申请号：US253216
申请日：1988-10-03
申请人： Hiroyuki Yamauchi , Toshio Yamada
发明人： Hiroyuki Yamauchi , Toshio Yamada
IPC分类号： G11C11/409 , G01R19/00 , G11C7/06 , H03K17/10 , H03K17/14
CPC分类号： G11C7/065 , H03K17/102 , H03K17/145
摘要： In order to enhance the sensitivity of a sense amplifier circuit, each one of the transistor pair composing the sense amplifier circuit is formed by transistors connected parallel in an even number of stages, and therefore the sense amplifier circuit is made of transistor pair having an extremely balanced characteristic, cancelling the asymmetricity of current-voltage characteristic of the transistor pair to null.
摘要翻译：为了提高读出放大器电路的灵敏度，构成读出放大器电路的晶体管对中的每一个由以偶数个级并联连接的晶体管形成，因此读出放大器电路由具有极高的晶体管对平衡特性，消除晶体管对的电流 - 电压特性的不对称性为零。

86. 发明授权

US07749950B2 Stain-proofing agent and building board using same 有权
标题翻译：防污剂和建筑板使用相同
公开(公告)号：US07749950B2
公开(公告)日：2010-07-06
申请号：US11480410
申请日：2006-07-05
申请人： Masanori Ukai , Hiroyuki Yamauchi , Yasuhisa Imanishi
发明人： Masanori Ukai , Hiroyuki Yamauchi , Yasuhisa Imanishi
IPC分类号： C11D1/00 , B32B18/00
CPC分类号： C09D4/00 , C04B14/062 , C04B18/146 , C04B41/009 , C04B41/5089 , C04B41/52 , C04B41/68 , C04B41/71 , C04B2111/2038 , Y02W30/94 , Y02W30/97 , Y10T442/2279 , C04B41/46 , C04B2103/408 , C04B41/463 , C04B41/4876 , C04B41/502 , C04B41/483 , C04B41/522 , C04B18/26 , C04B28/18
摘要： An object of the present invention is to provide a durable excellent stain-proofing property to the surface of a coating formed on a substrate surface of a building board without deteriorating the surface of the coating. The present invention also, provides a stain-proofing agent containing silica fine particles, an aqueous solvent and, as a stain-proofing improver, an alkali metal compound and/or an alkaline earth metal compound and/or a phosphorus compound and/or a clay mineral. The present invention also provides a building board having an excellent stain-proofing property prepared by applying a coating composition onto the surface of a substrate to form a coat, and then applying a stain-proofing agent onto the coat while the coat is in an unhardened state or applying a stain-proofing agent onto the coat after subjecting the coat to a roughening treatment to enhance the adhesion of the stain-proofing layer to the coat.
摘要翻译：本发明的目的是提供一种耐久性优异的防污染性能，而不会使涂层的表面劣化，从而在建筑板的基板表面上形成的涂层的表面具有良好的耐污染性。本发明还提供了含有二氧化硅微粒，水性溶剂和作为防污改良剂的碱金属化合物和/或碱土金属化合物和/或磷化合物和/或粘土矿物。本发明还提供了一种建筑板，其具有通过将涂料组合物涂布在基材表面上以形成涂层而制备的优异的防污性，然后在涂层处于未硬化的同时将防污剂施加到涂层上在使涂层进行粗糙化处理以增强防污层与涂层的粘附性之后，将涂布防污剂施加到涂层上。

87. 发明授权

US07379318B2 Semiconductor integrated circuit device and method for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07379318B2
公开(公告)日：2008-05-27
申请号：US11085579
申请日：2005-03-22
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C17/10 , G11C11/41
CPC分类号： H01L27/105 , G11C17/12
摘要： A semiconductor integrated circuit device includes a semiconductor substrate and a ROM region, an SRAM region and a peripheral circuit region which are formed on the semiconductor substrate. Further, a column switch region is provided adjacent to the ROM region. MOS transistors in the ROM region and channel regions of access transistors in the SRAM region have substantially the same p-type impurity concentration. Accordingly, the threshold voltages of the transistors are adjusted by making use of the great dependence of the threshold voltage of the transistor on the channel width.
摘要翻译：半导体集成电路器件包括形成在半导体衬底上的半导体衬底和ROM区域，SRAM区域和外围电路区域。此外，在ROM区域附近设置列开关区域。 ROM区域中的MOS晶体管和SRAM区域中的存取晶体管的沟道区域具有基本上相同的p型杂质浓度。因此，通过利用晶体管的阈值电压对通道宽度的很大依赖性来调节晶体管的阈值电压。

88. 发明申请

US20080011168A1 Printing apparatus and printing method for the same 审中-公开
标题翻译：印刷装置和印刷方法相同
公开(公告)号：US20080011168A1
公开(公告)日：2008-01-17
申请号：US11600281
申请日：2006-11-16
申请人： Hiroyuki Yamauchi , Tomoyoshi Yabe
发明人： Hiroyuki Yamauchi , Tomoyoshi Yabe
IPC分类号： B41F17/00
CPC分类号： B41J3/407
摘要： Horizontal joint portions of abutting building boards are constructed in a manner to look straight-line in an external appearance when constructed even in a case that the building board has a dimension error. A printing apparatus for printing a building board of a shiplap joint system composed of a design surface having a horizontal joint portion formed along a longitudinal direction of the building board and an upper and lower shiplap portions formed at an end portion of the building board includes a fixed printing head having a plurality of nozzles for performing printing operation by means of emitting a jet of ink toward the design surface of the building board, in which the printing head performs printing operation along a printing line spaced apart from an edge of the upper shiplap portion or the lower shiplap portion at a constant distance when performing the printing operation for the horizontal joint portion.
摘要翻译：邻接建筑板的水平接合部分，即使在建筑板具有尺寸误差的情况下构造成外观看起来也是直线的。一种用于印刷由沿着建筑板的纵向形成的具有水平接合部分的设计表面和形成在建筑物板的端部处的上部和下部遮光部分的设计表面组成的遮蔽物接合系统的建筑板的印刷设备包括：固定式打印头具有多个喷嘴，用于通过向构建板的设计表面喷射墨水来执行打印操作，其中打印头沿着与上部shiplap的边缘间隔开的打印线执行打印操作在执行水平接合部的打印操作时，以恒定的距离对部分或下部遮光部进行处理。

89. 发明授权

US07187596B2 Semiconductor system having a source potential supply section 有权
标题翻译：具有源极电位供应部分的半导体系统
公开(公告)号：US07187596B2
公开(公告)日：2007-03-06
申请号：US11097359
申请日：2005-04-04
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C8/08
摘要： A semiconductor system includes a plurality of memory systems (SARM, ROM, etc.) and circuit systems. The semiconductor system further includes an analog power supply circuit which is common to the memory systems. The analog power supply circuit supplies a source potential to word line drivers of the memory systems. The source potential is set to a potential different from a ground potential and a supply voltage of the semiconductor system.
摘要翻译：半导体系统包括多个存储器系统（SARM，ROM等）和电路系统。半导体系统还包括对于存储器系统是共同的模拟电源电路。模拟电源电路为存储器系统的字线驱动器提供源极电位。源极电位被设定为与半导体系统的接地电位和电源电压不同的电位。

90. 发明申请

US20070002662A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070002662A1
公开(公告)日：2007-01-04
申请号：US11476566
申请日：2006-06-29
申请人： Yoshinobu Yamagami , Hiroyuki Yamauchi
发明人： Yoshinobu Yamagami , Hiroyuki Yamauchi
IPC分类号： G11C5/14
CPC分类号： G11C11/413
摘要： A semiconductor memory device, including a memory cell including a flip-flop, and a memory cell power supply circuit for supplying a cell power supply voltage to the memory cell, wherein the memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period.
摘要翻译：一种半导体存储器件，包括具有触发器的存储单元和用于向存储单元提供单元电源电压的存储单元电源电路，其中存储单元电源电路将第一单元电源电压周期和不同的单元电源电压。

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