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81. 发明授权

US07109093B2 Crackstop with release layer for crack control in semiconductors 失效
标题翻译：具有半导体裂纹控制释放层的裂纹
公开(公告)号：US07109093B2
公开(公告)日：2006-09-19
申请号：US10708735
申请日：2004-03-22
申请人： John A. Fitzsimmons , Michael W. Lane , Vincent J. McGahay , Thomas M. Shaw , Anthony K. Stamper
发明人： John A. Fitzsimmons , Michael W. Lane , Vincent J. McGahay , Thomas M. Shaw , Anthony K. Stamper
IPC分类号： H01L21/76 , H01L21/82
CPC分类号： H01L23/562 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming and the integrated circuit device structure formed having vertical interfaces adjacent an existing crack stop around a perimeter of a chip, whereby the vertical interface controls cracks generated during side processing of the device such as dicing, and in service from penetrating the crack stop. The vertical interface is comprised of a material that prevents cracks from damaging the crack stop by deflecting cracks away from penetrating the crack stop, or by absorbing the generated crack energies. Alternatively, the vertical interface may be a material that allows advancing cracks to lose enough energy such that they become incapable of penetrating the crack stop. The present vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material.
摘要翻译：形成方法和集成电路器件结构形成，具有与现有裂纹相邻的垂直接口围绕芯片的周边，由此垂直接口控制器件的侧面处理期间产生的裂纹，例如切割，并且在穿透裂缝停止。垂直界面由防止裂纹破坏裂纹的材料组成，通过使裂纹偏离穿透裂缝，或通过吸收所产生的裂纹能量来防止裂纹破裂。或者，垂直界面可以是允许前进裂纹失去足够的能量使得它们不能穿透裂缝停止的材料。现有的垂直接口可以以多种方式实现，例如释放材料的垂直间隔物，释放材料的垂直沟槽或释放材料的垂直通道。

82. 发明授权

US06914320B2 Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof 有权
标题翻译：双层HDP CVD / PE CVD帽在先进的BEOL互连结构及其方法
公开(公告)号：US06914320B2
公开(公告)日：2005-07-05
申请号：US10807029
申请日：2004-03-23
申请人： Tze-Chiang Chen , Brett H. Engel , John A. Fitzsimmons , Terence Kane , Naftall E. Lustig , Ann McDonald , Vincent McGahay , Soon-Cheon Seo , Anthony K. Stamper , Yun Yu Wang , Erdem Kaltalioglu
发明人： Tze-Chiang Chen , Brett H. Engel , John A. Fitzsimmons , Terence Kane , Naftall E. Lustig , Ann McDonald , Vincent McGahay , Soon-Cheon Seo , Anthony K. Stamper , Yun Yu Wang , Erdem Kaltalioglu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.
摘要翻译：公开了一种先进的后端（BEOL）金属化结构。该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由介电材料形成，优选沉积通过等离子体增强化学气相沉积（PE CVD）工艺。还公开了一种用于形成BEOL金属化结构的方法。本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

83. 发明授权

US06838355B1 Damascene interconnect structures including etchback for low-k dielectric materials 失效
标题翻译：大马士革互连结构，包括低k电介质材料的回蚀
公开(公告)号：US06838355B1
公开(公告)日：2005-01-04
申请号：US10604602
申请日：2003-08-04
申请人： Anthony K. Stamper , Edward C. Cooney, III , Jeffrey P. Gambino , Timothy J. Dalton , John A. Fitzsimmons , Lee M. Nicholson
发明人： Anthony K. Stamper , Edward C. Cooney, III , Jeffrey P. Gambino , Timothy J. Dalton , John A. Fitzsimmons , Lee M. Nicholson
IPC分类号： H01L21/31 , H01L21/3205 , H01L21/76 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76849 , H01L21/76801 , H01L21/76804 , H01L21/76807 , H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L21/76852 , H01L21/76885 , H01L23/5222 , H01L23/53228 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for forming back-end-of-line (BEOL) interconnect structures in disclosed. The method and resulting structure includes etchback for low-k dielectric materials. Specifically, a low dielectric constant material is integrated into a dual or single damascene wiring structure which contains a dielectric material having relatively high dielectric constant (i.e., 4.0 or higher). The damascene structure comprises the higher dielectric constant material immediately adjacent to the metal interconnects, thus benefiting from the mechanical characteristics of these materials, while incorporating the lower dielectric constant material in other areas of the interconnect level.
摘要翻译：公开的形成后端（BEOL）互连结构的方法。该方法和结果包括低k电介质材料的回蚀。具体地说，将低介电常数材料整合到双或单镶嵌布线结构中，该结构包含介电常数（即4.0或更高）的介电材料。镶嵌结构包括紧邻金属互连件的较高介电常数材料，从而受益于这些材料的机械特性，同时将较低介电常数材料结合在互连级别的其他区域。

84. 发明授权

US06617690B1 Interconnect structures containing stress adjustment cap layer 有权
标题翻译：互连结构包含应力调整盖层
公开(公告)号：US06617690B1
公开(公告)日：2003-09-09
申请号：US10218292
申请日：2002-08-14
申请人： Stephen M. Gates , Timothy J. Dalton , John A. Fitzsimmons
发明人： Stephen M. Gates , Timothy J. Dalton , John A. Fitzsimmons
IPC分类号： H01L2940
CPC分类号： H01L23/53295 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.
摘要翻译：本文提供了具有用于半导体器件的相对低的内应力和介电常数的新型互连结构。新颖的互连结构包括具有大于约20ppm的热膨胀系数的第一层和与其相关联的第一内部应力，第一层具有形成在其中的第一组金属线; 具有小于约20ppm的热膨胀系数的第二层和与其相关联的第二内应力，所述第二层在其中形成有第二组金属线; 以及形成在所述第一层和所述第二层之间的一个或多个应力调整盖层，所述盖层具有第三内应力以抵消所述第一层的第一应力和所述第二层的所述第二应力，并诱导有利的减轻互连结构上的应力。还提供了制造具有显着降低的内部应力的半导体器件的方法。

85. 发明授权

US06493078B1 Method and apparatus to improve coating quality 有权
标题翻译：提高涂料质量的方法和设备
公开(公告)号：US06493078B1
公开(公告)日：2002-12-10
申请号：US09956367
申请日：2001-09-19
申请人： John A. Fitzsimmons , Darryl D. Restaino , Michael J. Schade
发明人： John A. Fitzsimmons , Darryl D. Restaino , Michael J. Schade
IPC分类号： G01N2100
CPC分类号： G01N21/9501 , G01N21/9503 , G01N2021/8427
摘要： A method and structure for improving a coating on a substrate comprises a chamber further comprising a rotatable holder, which holds the substrate; a supply of coating material for coating the substrate in the chamber; a window in the wall of the chamber; and a supply of liquid for coating at least a portion of the window on the interior side of the chamber. The chamber is preferably adapted to house the window in multiple configurations. A camera (or other optical detector), which is positioned outside of the chamber, monitors the substrate through the window.
摘要翻译：用于改善衬底上的涂层的方法和结构包括：腔室，其还包括保持衬底的可旋转保持器; 供应用于在所述室中涂覆所述基材的涂料; 在房间的墙壁上的一个窗口; 以及用于在室的内侧涂覆窗口的至少一部分的液体供应。该室优选适于将窗户容纳在多种构型中。位于室外的相机（或其他光学检测器）通过窗口监测基板。

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