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81. 发明专利

JPS5580161A NORMALLY MONITORING SYSTEM OF MICROCOMPUTER 失效
公开(公告)号：JPS5580161A
公开(公告)日：1980-06-17
申请号：JP15307878
申请日：1978-12-13
申请人： HITACHI LTD
发明人： CHIBA TOMIO , SAKOU EIZABUROU , SANO KAZUO
IPC分类号： G06F11/30
摘要： PURPOSE:To monitor normally a microcomputer independently of other system constitutions by causing a CPU to execute the program of an instruction circuit on the margin time of the operation processing for every sample of the microcomputer and comparing results in a comparator circuit. CONSTITUTION:A unit which is constituted by an operation processing circuit, a program recording circuit, a data recording circuit and an I/O circuit and monitors normally the microcomputer, which subjects system information digitized and inputted from the object system to the operation processing at every sampling time and outputs required results, is provided with instruction circuit 10 where a program to check functions of operation results of CPU1 is stored. Further, comparator circuit 2 is provided which decides results of program execution for correctness when the program of instruction circuit 10 is executed by CPU1, and the operation processing of the program of instruction circuit 10 is executed by CPU1 on the margin time of the operation processing for every sampling under the control of I104 which inputs and outputs data, and normalcy of operation results are checked by circuit 20.

82. 发明专利

JPS5518843A PROTECTIVE RELAY 失效
公开(公告)号：JPS5518843A
公开(公告)日：1980-02-09
申请号：JP9145378
申请日：1978-07-28
申请人： HITACHI LTD
发明人： CHIBA TOMIO , SASAKI HIROSHI , MAKINO JIYUNICHI
IPC分类号： H02H3/40 , H02H3/38

83. 发明专利

JPS5513642A PROTECTIVE RELAY FOR COMPUTER 失效
公开(公告)号：JPS5513642A
公开(公告)日：1980-01-30
申请号：JP8515278
申请日：1978-07-14
申请人： HITACHI LTD
发明人： CHIBA TOMIO , KUDOU HIROYUKI , SANO KAZUO
IPC分类号： H04L1/00 , G05B9/02 , G05B23/02 , H02H3/02 , H02H3/05 , H02H3/28 , H02H3/40

84. 发明专利

JPS54156148A DIGITAL PROTECTIVE RELAY 失效
公开(公告)号：JPS54156148A
公开(公告)日：1979-12-08
申请号：JP6538478
申请日：1978-05-31
申请人： HITACHI LTD
发明人： SAKAWA EIZABUROU , SANO KAZUO , CHIBA TOMIO
IPC分类号： H02H7/04 , H02H3/40
摘要： PURPOSE:To reduce requierd memouy capacity in the trouble discriminating information by controlling the weight of bit in address assigning information for the value of electricity as digitalized data including voltage and current in the power system corresponding to memory divisions varied in the protection range. CONSTITUTION:Plural-stage protection areas Z1 to Z3 as illustrated are provided for selective protection of trouble divisions of the system. The resistance value R and the reactance X in the system is determined in a computation circuit 1 from the data such as input voltage and current and the output of the value R is given direct to an address assigning circuit 3. On the other hand, the input of the value X is compared with a specified value K (the minimum value of X in the area Z3) by a comparison circuit of an address correction circuit 2. The value is sent intact to an address assinging circuit 4 when X K. Thus, depending on the output of the address assinging circuit, the address of a memory circuit 5 is assigned. This can eliminate errors in reading out of information due to the difference in the mesh lenght in the X axis between the area Z3 and Z1, thereby reducing the required memory capacity.

85. 发明专利

JPS5474602A PHOTO DELIVERY UNIT OF SYNCHRONOUS TYPE 失效
公开(公告)号：JPS5474602A
公开(公告)日：1979-06-14
申请号：JP14161277
申请日：1977-11-28
申请人： HITACHI LTD
发明人： KUDOU HIROYUKI , SANO KAZUO , MIKI YOSHITERU , CHIBA TOMIO
IPC分类号： H04B10/00 , H04L5/14
摘要： PURPOSE:To reduce the number of optical fibers and to reduce the cost without lowering the reliability, by delivering the synchronous signal at vacant time of data through the use of optical fiber of one core and of the optical branch inserter. CONSTITUTION:The synchronous signal is converted into optical signal with the transmitter 1, is fed to the optical branch inserter 8 via the fiber 21, and the output is propagated to the fiber 9. The synchronous signal restored with the receiver 3 via the optical branch inserter 10 and the fiber 61 is fed to the data input unit 4, synchronizing the sampling clock of the oscillator output incorporated in the unit 4. Further, the output data of the unit 4 is delivered to the central unit via the transmitter 5, fiber 9 and the receiver 7.

86. 发明专利

JPS5438702A OPTICAL TRANSMISSION DEVICE 失效
公开(公告)号：JPS5438702A
公开(公告)日：1979-03-23
申请号：JP10487877
申请日：1977-09-02
申请人： HITACHI LTD
发明人： KUDOU HIROYUKI , SANO KAZUO , CHIBA TOMIO
IPC分类号： H04B10/03 , H04B10/032 , H04B10/079
摘要： PURPOSE:To avoid the fault occurrence due to the life time of the light source as well as to prevent the deterioration the system reliability for the optical communication equipment, by switching the power source via the timer.

87. 发明专利

JPS5425380A DIGITAL CONTROLLER 失效
公开(公告)号：JPS5425380A
公开(公告)日：1979-02-26
申请号：JP9029377
申请日：1977-07-29
申请人： HITACHI LTD
发明人： SANO KAZUO , KUDOU HIROYUKI , CHIBA TOMIO , MIKI YOSHITERU
IPC分类号： G05B1/03 , H02H7/26
摘要： PURPOSE:To provide a digital controller enabling for achieving the same time sampling of data available from the different locations with the system control actuation based on the data supplied from a plurality of data sources whose locations are setting apart.

88. 发明专利

JPS5416946A DATA TRANSFER DEVICE 失效
公开(公告)号：JPS5416946A
公开(公告)日：1979-02-07
申请号：JP8107477
申请日：1977-07-08
申请人： HITACHI LTD
发明人： CHIBA TOMIO , SANO KAZUHIRO
IPC分类号： G06F17/40
摘要： PURPOSE:To secure the aligned memorization of the data which is memorized in the non-continuous address into another memory unit via ROM memorizing the storage sequence.

89. 发明专利

JPS5394146A MULTIPLICATION SYSTEM 失效
公开(公告)号：JPS5394146A
公开(公告)日：1978-08-17
申请号：JP776377
申请日：1977-01-28
申请人： HITACHI LTD
发明人： CHIBA TOMIO , SAKOU EIZABUROU
IPC分类号： G06F7/533 , G06F7/508 , G06F7/527
摘要： PURPOSE:To ensure a high-speed multiplication process by storing the multiplier in the shift register, securing a harmonious action for the shift timing between the shift tegister and ALU (arithmetic logic unit) and controlling the operation step by the adjacent lower two bits of the shift register.

90. 发明专利

JPS5379338A MULTIPLICATION SYSTEM 失效
公开(公告)号：JPS5379338A
公开(公告)日：1978-07-13
申请号：JP15496076
申请日：1976-12-24
申请人： HITACHI LTD
发明人： CHIBA TOMIO , SANO KAZUO , SAKOU EIZABUROU
IPC分类号： G06F7/53 , G06F7/527 , G06F7/533
摘要： PURPOSE:To operate negative maximum value 2 -which can be expressed by operation bit width m of the computer-by improving the logical equipment of the multiplier circuit due to Boolean method when the multiplication processing is performed by using an arithmetic operation circuit.

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