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81. 发明申请

US20050227426A1 CHARGE-TRAPPING MEMORY CELL ARRAY AND METHOD FOR PRODUCTION 失效
标题翻译：电荷捕获存储单元阵列和生产方法
公开(公告)号：US20050227426A1
公开(公告)日：2005-10-13
申请号：US10815223
申请日：2004-03-31
申请人： Joachim Deppe , Josef Willer
发明人： Joachim Deppe , Josef Willer
IPC分类号： H01L21/8246 , H01L27/115 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11568
摘要： In a memory cell array comprising charge-trapping memory cells, local interconnects along the direction of the wordlines for connecting source/drain regions of adjacent memory cells to bitlines are formed by selective deposition of silicon or polysilicon bridges at sidewalls of the semiconductor material within upper recesses in the dielectric material of shallow trench isolations running across the wordlines.
摘要翻译：在包括电荷捕获存储器单元的存储单元阵列中，沿用于将相邻存储器单元的源极/漏极区域连接到位线的字线方向的局部互连通过在上部的半导体材料的侧壁上选择性沉积硅或多晶硅桥来形成浅沟槽隔离物的电介质材料中的凹槽穿过字线。

82. 发明申请

US20050164456A1 Method for fabricating an NROM memory cell array 有权
标题翻译：制造NROM存储单元阵列的方法
公开(公告)号：US20050164456A1
公开(公告)日：2005-07-28
申请号：US11023041
申请日：2004-12-27
申请人： Joachim Deppe , Christoph Kleint , Christoph Ludwig , Josef Willer
发明人： Joachim Deppe , Christoph Kleint , Christoph Ludwig , Josef Willer
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L29/66833
摘要： In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (2), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer (16) is reached, and afterward a polysilicon layer (18), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.
摘要翻译：在该方法中，蚀刻沟槽，并且在其间，位线（8）分别布置在掺杂的源极/漏极区域（3,4）上。存储层（5,6,7）被施加，栅电极（2）布置在沟槽壁处。在向栅极电极（2）引入向多个沟槽中引入的多晶硅之后，以平坦化的方式将顶面进行研磨，直到到达覆盖层（16）的顶侧，然后将多晶硅层（18），其被设置用于字线，并且被图案化以形成字线。

83. 发明申请

US20050085037A1 Method for fabricating NROM memory cells with trench transistors 有权
标题翻译：用沟槽晶体管制造NROM存储单元的方法
公开(公告)号：US20050085037A1
公开(公告)日：2005-04-21
申请号：US11006049
申请日：2004-12-07
申请人： Christoph Kleint , Christoph Ludwig , Josef Willer , Joachim Deppe
发明人： Christoph Kleint , Christoph Ludwig , Josef Willer , Joachim Deppe
IPC分类号： H01L29/41 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115
摘要： An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n+-type well (19) for the source/drain regions, the bit line layer (3, 4) is patterned using an etching stop layer (2) arranged on the semiconductor body (1).
摘要翻译：在沟槽被蚀刻到半导体材料之前，将导电位线层施加并图案化成彼此平行布置的部分，在这种情况下，在位线层（3,4）的图案化之后并且在蚀刻引入注入用于限定结的位置，或者在用于源极/漏极区的n + H +型阱（19）的注入之后，位线层（3,4）使用布置在半导体本体（1）上的蚀刻停止层（2）进行图案化。

84. 发明授权

US06777725B2 NROM memory circuit with recessed bitline 有权
标题翻译：带凹槽位线的NROM存储电路
公开(公告)号：US06777725B2
公开(公告)日：2004-08-17
申请号：US10171643
申请日：2002-06-14
申请人： Josef Willer , Herbert Palm
发明人： Josef Willer , Herbert Palm
IPC分类号： H01L29768
CPC分类号： H01L27/11568 , H01L27/115
摘要： An integrated memory circuit of the type of an NROM memory includes recessed bit lines formed of a material having a low ohmic resistance. By recessing the bit lines with respect to the semiconductor substrate surface of a peripheral controlling circuit for an array of memory cells allows to form the word line lithography on a perfect or almost perfect plane so that the word line formation results in a production with higher yield and, therefore, lower costs for the individual integrated memory circuit.
摘要翻译： NROM存储器类型的集成存储器电路包括由具有低欧姆电阻的材料形成的凹陷位线。通过将相对于用于存储单元阵列的外围控制电路的半导体衬底表面的位线凹进，可以在完美或几乎完美的平面上形成字线光刻，使得字线形成导致具有更高产量的生产因此，单个集成存储器电路的成本较低。

85. 发明授权

US06627940B1 Memory cell arrangement 失效
标题翻译：存储单元布置
公开(公告)号：US06627940B1
公开(公告)日：2003-09-30
申请号：US09937838
申请日：2002-02-05
申请人： Dirk Schumann , Bernhard Sell , Hans Reisinger , Josef Willer
发明人： Dirk Schumann , Bernhard Sell , Hans Reisinger , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823
摘要： A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.
摘要翻译：存储单元阵列包括形成平行的第一和第二沟槽的衬底。晶体管的上部源极/漏极区域邻接第一和第二个第二沟槽中的两个，并且位于其下部源极/漏极区域的上方。与晶体管相关联的第一沟槽中的导电结构在其第一边缘邻接上部源极/漏极区。相关联的第一沟槽中的绝缘结构将导电结构与相关联的第一沟槽的第二边缘和底部绝缘。在其上是另一个绝缘层的字线在上部/源极漏极区域上方并且平行于相关联的第一沟槽凸起进入第二沟槽。绝缘空间横向与字线连接。导电结构上的与上部源极/漏极区域电连通的触点与电容器连接。

86. 发明授权

US06548861B2 Memory cell, memory cell arrangement and fabrication method 有权
标题翻译：存储单元，存储单元布置和制造方法
公开(公告)号：US06548861B2
公开(公告)日：2003-04-15
申请号：US09900649
申请日：2001-07-06
申请人： Herbert Palm , Josef Willer
发明人： Herbert Palm , Josef Willer
IPC分类号： H09L2996
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L29/66833
摘要： An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.
摘要翻译：导电层或层序列优选地包括施加到金属硅化物或多晶硅层的含金属层以降低掩埋位线的电阻。层或层序列已经以带状形式图案化，以对应于位线，并且布置在具有ONO存储层序列的存储晶体管的源极/漏极区域和布置在沟槽中的栅极电极。金属硅化物优选为硅化钴，并且含金属层优选为硅化钨或WN / W。

87. 发明授权

US06525363B1 Integrated circuit configuration with at least one capacitor and method for producing the same 有权
标题翻译：具有至少一个电容器的集成电路配置及其制造方法
公开(公告)号：US06525363B1
公开(公告)日：2003-02-25
申请号：US09677433
申请日：2000-10-02
申请人： Josef Willer , Bernhard Sell , Dirk Schumann
发明人： Josef Willer , Bernhard Sell , Dirk Schumann
IPC分类号： H01L27108
CPC分类号： H01L28/84 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L28/86 , H01L28/90
摘要： A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).
摘要翻译：设置在基板（1）的表面上的电容器的第一电容电极具有布置在其上的下部（T）和侧部（S）。横向部分（S）的至少第一横向区域以这样的方式波动，使得其具有沿着平行于基底（1）的表面的平面中的每条线条沿着线形成的凸起和凹陷。横向部分（T）可以通过将导电材料沉积在层中产生的凹陷（V）中来制造，层的顺序是层，其层由第一材料和第二材料交替组成，并且其中第一材料经受湿蚀刻相对于第二材料选择性地到达第一深度。第一电容器电极设置有电容器电介质（KD）。第二电容器电极（P）与电容器电介质（KD）相邻。

88. 发明授权

US06222753B1 SRAM cell arrangement and method for manufacturing same 有权
标题翻译： SRAM单元布置及其制造方法
公开(公告)号：US06222753B1
公开(公告)日：2001-04-24
申请号：US09446419
申请日：1999-12-20
申请人： Bernd Goebel , Emmerich Bertagnolli , Josef Willer , Barbara Hasler , Paul-Werner von Basse
发明人： Bernd Goebel , Emmerich Bertagnolli , Josef Willer , Barbara Hasler , Paul-Werner von Basse
IPC分类号： G11C700
CPC分类号： H01L27/11 , H01L27/1104
摘要： An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.
摘要翻译：每个存储单元包括六个MOS晶体管的SRAM单元布置，其中每个晶体管形成为垂直晶体管。 MOS晶体管布置在沟槽的侧壁。存储单元的部分，例如栅极电极或形成为间隔物的导电结构，经由布置在衬底表面上方的相邻的水平导电结构接触。存储器单元的部分之间的连接通过布置在凹陷和字线的侧壁处的第三导电结构经由第一位线经由第二位线和/或通孔的扩散区域经由衬底内的凹陷的侧壁相邻布置相对于垂直于表面的轴部分地布置在不同高度的导电结构。触头同时接触MOS晶体管的多个部分。

89. 发明授权

US6033534A Method for producing an Al-containing layer with a planar surface on a substrate having hole structures with a high aspect ratio in the surface 失效
标题翻译：在具有在表面上具有高纵横比的孔结构的基板上制造具有平坦表面的含Al层的方法
公开(公告)号：US6033534A
公开(公告)日：2000-03-07
申请号：US54200
申请日：1993-04-30
申请人： Josef Willer , Hermann Wendt , Volker Lehmann
发明人： Josef Willer , Hermann Wendt , Volker Lehmann
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/334 , C23C14/34
CPC分类号： H01L29/66181 , H01L21/28512
摘要： A method for producing an Al-containing layer having a planar surface onto a substrate having hole structures with high aspect ratios formed in the surface of the substrate, wherein the Al-containing layer is applied in a sputtering process during which the substrate is held at an elevated temperature and the sputtering process is implemented at a pressure between 1.3.times.10.sup.-2 Pa and 13 Pa and at a low partial gas pressure. The substrate can be held at a temperature between approximately 400.degree. C. and 500.degree. C. during the sputtering process. A partial residual gas pressure of less than 1.3.times.10.sup.-5 PA can prevail in the vacuum. An intermediate layer of pure titanium and a barrier layer of TiN can be directly deposited onto the substrate and the Al-containing layer can then be applied onto this intermediate end barrier layer.
摘要翻译：一种在基板的表面形成具有高纵横比的孔结构的基板上的具有平坦表面的含Al层的方法，其中所述含Al层以基板保持在其中的溅射工艺升高的温度和溅射过程在1.3×10 -2 Pa至13 Pa之间的压力下和在低的部分气体压力下实施。在溅射过程中，衬底可保持在约400℃至500℃的温度。小于1.3×10-5PA的部分残余气体压力可以在真空中占优势。可以将纯钛的中间层和TiN的阻挡层直接沉积到衬底上，然后将含Al层施加到该中间阻挡层上。

90. 发明授权

US5306647A Method for manufacturing a solar cell from a substrate wafer 失效
标题翻译：从基板晶片制造太阳能电池的方法
公开(公告)号：US5306647A
公开(公告)日：1994-04-26
申请号：US998611
申请日：1992-12-30
申请人： Volker Lehmann , Reinhard Stengl , Hermann Wendt , Wolfgang Hoenlein , Josef Willer
发明人： Volker Lehmann , Reinhard Stengl , Hermann Wendt , Wolfgang Hoenlein , Josef Willer
IPC分类号： C25F3/12 , H01L21/3063 , H01L31/0352 , H01L31/047 , H01L31/18
CPC分类号： H01L31/1804 , H01L21/3063 , H01L31/03529 , H01L31/047 , Y02E10/547 , Y02P70/521
摘要： A self-supporting layer of n-doped monocrystalline silicon is stripped from a substrate wafer of n-doped, monocrystalline silicon by electrochemical etching for manufacturing a solar cell. Holes are formed in the substrate wafer by electrochemical etching, particularly in a fluoride-containing, acidic electrolyte wherein the substrate wafer is connected as an anode. When a depth of the holes that essentially corresponds to the thickness of the self-supporting layer is reached, the process parameters of the etching are modified such that the self-supporting layer is stripped as a consequence of the holes growing together. The solar cell is manufactured from the self-supporting layer, and the method can be applied repeatedly on the same substrate wafer for stripping a plurality of self-supporting layers.
摘要翻译：通过用于制造太阳能电池的电化学蚀刻，从n掺杂的单晶硅的衬底晶片剥离n掺杂单晶硅的自支撑层。通过电化学蚀刻，特别是在其中衬底晶片作为阳极连接的含氟化物的酸性电解质中，在衬底晶片中形成孔。当达到基本上对应于自支撑层的厚度的孔的深度时，蚀刻的工艺参数被修改，使得自支撑层由于孔一起生长而被剥离。该太阳能电池由自支撑层制造，并且可以在相同的基板晶片上重复地施加该方法以剥离多个自支撑层。

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