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81. 发明授权

US08754476B2 High voltage device and manufacturing method thereof 有权
标题翻译：高压器件及其制造方法
公开(公告)号：US08754476B2
公开(公告)日：2014-06-17
申请号：US13185951
申请日：2011-07-19
申请人： Tsung-Yi Huang
发明人： Tsung-Yi Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L29/0696 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a well of a substrate. The high voltage device includes: a field oxide region; a gate, which is formed on a surface of the substrate, and part of the gate is located above the field oxide region; a source and a drain, which are formed at two sides of the gate respectively; and a first low concentration doped region, which is formed beneath the gate and has an impurity concentration which is lower than that of the well surrounded, wherein from top view, the first low concentration doped region has an area within the gate and not larger than an area of the gate, and the first low concentration doped region has a depth which is deeper than that of the source and drain.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在衬底的阱中。高电压装置包括：场氧化物区域; 栅极，其形成在基板的表面上，栅极的一部分位于场氧化物区域的上方; 源极和漏极，分别形成在栅极的两侧; 以及第一低浓度掺杂区，其形成在栅极下方并且具有低于所围绕的阱的杂质浓度，其中从顶视图来看，第一低浓度掺杂区具有栅极内的面积并且不大于栅极的面积，第一低浓度掺杂区域的深度比源极和漏极深。

82. 发明授权

US08728895B1 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
标题翻译：双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US08728895B1
公开(公告)日：2014-05-20
申请号：US14146528
申请日：2014-01-02
申请人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
发明人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L21/336
CPC分类号： H01L29/4238 , H01L21/28114 , H01L21/823425 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS设备包括：用于定义设备区域的隔离结构; 具有环形结构的门; 位于环外的排水沟; 以及位于环内的轻掺杂漏极，源极和体电极。为了增加栅极角落处的次阈值电压，角部完全位于隔离结构上，或者轻掺杂漏极与角分开预定距离。

83. 发明申请

US20140120679A1 DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：双重扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US20140120679A1
公开(公告)日：2014-05-01
申请号：US14146528
申请日：2014-01-02
申请人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
发明人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L21/28 , H01L29/66
CPC分类号： H01L29/4238 , H01L21/28114 , H01L21/823425 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS设备包括：用于定义设备区域的隔离结构; 具有环形结构的门; 位于环外的排水沟; 以及位于环内的轻掺杂漏极，源极和体电极。为了增加栅极角落处的次阈值电压，角部完全位于隔离结构上，或者轻掺杂漏极与角分开预定距离。

84. 发明授权

US08685824B2 Hybrid high voltage device and manufacturing method thereof 有权
标题翻译：混合高压器件及其制造方法
公开(公告)号：US08685824B2
公开(公告)日：2014-04-01
申请号：US13529963
申请日：2012-06-21
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/7817 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/402 , H01L29/42368 , H01L29/4238 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.
摘要翻译：本发明公开了一种混合式高压装置及其制造方法。混合高压器件形成在第一导电型衬底中，并且包括至少一个横向双扩散金属氧化物半导体（LDMOS）器件区域和至少一个通气器件区域，其中LDMOS器件区域和通气器件区域被连接在宽度方向上以交替的顺序布置。此外，LDMOS器件区域和通风装置区域的相应的高压井，源极，漏极，体区和栅极分别彼此连接。

85. 发明申请

US20140061786A1 Double Diffused Metal Oxide Semiconductor Device and Manufacturing Method Thereof 审中-公开
标题翻译：双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US20140061786A1
公开(公告)日：2014-03-06
申请号：US13603385
申请日：2012-09-04
申请人： Tsung-Yi Huang , Chien-Wei Chiu
发明人： Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66681 , H01L29/063 , H01L29/0696 , H01L29/1083 , H01L29/42368 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes a first conductive type substrate, a second conductive type high voltage well, a first conductive type deep buried region, a field oxide region, a first conductive type body region, a gate, a second conductive type source, and a second conductive type drain. The deep buried region is formed below the high voltage well with a gap in between, and the gap is not less than a predetermined distance.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括第一导电型衬底，第二导电型高电压阱，第一导电类型深埋入区域，场氧化物区域，第一导电类型体区域，栅极，第二导电型源极和第二导电类型源极导电型漏极。深埋区域形成在高压井的下方，间隙为间隙，间隙不小于预定距离。

86. 发明申请

US20140015008A1 Transient Voltage Suppressor Circuit, and Diode Device Therefor and Manufacturing Method Thereof 有权
标题翻译：瞬态电压抑制器电路及其二极管器件及其制造方法
公开(公告)号：US20140015008A1
公开(公告)日：2014-01-16
申请号：US13549501
申请日：2012-07-15
申请人： Tsung-Yi Huang , Jin-Lian Su
发明人： Tsung-Yi Huang , Jin-Lian Su
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L29/66136 , H01L21/265 , H01L21/76224 , H01L27/0255 , H01L27/0814 , H01L29/0649
摘要： The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.
摘要翻译：本发明公开了一种瞬态电压抑制器（TVS）电路及其二极管装置及其制造方法。 TVS电路用于耦合到受保护电路以限制输入到保护电路的瞬态电压的幅度。 TVS电路包括抑制器装置和至少二极管装置。二极管器件形成在衬底中，其包括：在衬底中形成的阱; 形成在所述上表面下方的分离区域; 阳极区域和阴极区域，其分别形成在上表面下方的分离区域的两侧，其中阳极区域和阴极区域被分离区域分离; 以及掩埋层，其形成在阱下方的衬底中，具有较高的杂质密度和与该阱相同的导电类型。

87. 发明授权

US08592923B2 Coupling well structure for improving HVMOS performance 有权
公开(公告)号：US08592923B2
公开(公告)日：2013-11-26
申请号：US13280035
申请日：2011-10-24
申请人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
发明人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/28 , H01L29/1045 , H01L29/36 , H01L29/66128 , H01L29/66659 , H01L29/7835 , H01L29/8611
摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

88. 发明申请

US20130256846A1 Semiconductor Overlapped PN Structure and Manufacturing Method Thereof 有权
标题翻译：半导体重叠PN结构及其制造方法
公开(公告)号：US20130256846A1
公开(公告)日：2013-10-03
申请号：US13864196
申请日：2013-04-16
申请人： Tsung-Yi Huang , Chien-Hao Huang , Ying-Shiou Lin
发明人： Tsung-Yi Huang , Chien-Hao Huang , Ying-Shiou Lin
IPC分类号： H01L29/06
CPC分类号： H01L29/06 , H01L21/266 , H01L29/0688 , H01L29/36
摘要： The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.
摘要翻译：本发明公开了半导体重叠PN结构及其制造方法。该方法包括：提供衬底; 提供第一掩模以限定所述衬底中的P（或N）型阱和至少一个重叠区域; 将P（或N）型杂质注入P（或N）型阱和至少一个重叠区域; 提供具有至少一个开口的第二掩模，以在所述衬底中限定N（或P）型阱，并且在所述至少一个重叠区域中限定至少一个双注入区域; 将N（或P）型杂质注入N（或P）型阱和至少一个双注入区，使得至少一个双注入区具有P型和N型杂质。

89. 发明申请

US20130207185A1 ISOLATED DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：隔离装置及其制造方法
公开(公告)号：US20130207185A1
公开(公告)日：2013-08-15
申请号：US13370691
申请日：2012-02-10
申请人： Tsung-Yi Huang , Chien-Wei Chiu
发明人： Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/086 , H01L29/0611 , H01L29/0615 , H01L29/0619 , H01L29/0847 , H01L29/1083 , H01L29/66492 , H01L29/66659 , H01L29/7835
摘要： An isolated device is formed in a substrate in which is formed a high voltage device. The isolated device includes: an isolated well formed in the substrate by a lithography process and an ion implantation process used in forming the high voltage device; a gate formed on the substrate; a source and a drain, which are located in the isolated well at both sides of the gate respectively; a drift-drain region formed beneath the substrate surface, wherein the gate and the drain are separated by the drift-drain region, and the drain is in the drift-drain region; and a mitigation region, which is formed in the substrate and has a shallowest portion located at least below 90% of a depth of the drift-drain region as measured from the substrate surface, wherein the mitigation region and the drift-drain region are defined by a same lithography process.
摘要翻译：隔离器件形成在形成高电压器件的衬底中。隔离装置包括：通过光刻工艺在衬底中形成的隔离阱和用于形成高压器件的离子注入工艺; 形成在基板上的栅极; 源极和漏极分别位于门的两侧的隔离井中; 形成在所述衬底表面下方的漂移漏极区，其中所述栅极和所述漏极由所述漂移 - 漏极区分离，并且所述漏极在所述漂移 - 漏极区中; 以及缓解区域，其形成在所述衬底中，并且具有位于所述衬底表面测量的至少位于所述漂移 - 漏极区域的深度的90％以下的最浅部分，其中所述缓解区域和所述漂移 - 漏极区域被限定通过相同的光刻工艺。

90. 发明申请

US20130069153A1 High Voltage Device and Manufacturing Method Thereof 有权
标题翻译：高压器件及其制造方法
公开(公告)号：US20130069153A1
公开(公告)日：2013-03-21
申请号：US13235366
申请日：2011-09-17
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L21/823418 , H01L29/0634 , H01L29/0692 , H01L29/0886 , H01L29/1045 , H01L29/41758 , H01L29/423 , H01L29/66659 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.
摘要翻译：本发明公开了一种高压器件及其制造方法。高电压装置包括：具有用于限定器件区域的隔离结构的衬底; 位于所述器件区域中的漂移区域，其中，从顶视图，所述漂移区域包括彼此分离但彼此电连接的多个子区域; 设备区域中的源极和漏极; 以及在衬底的表面上以及器件区域中的源极和漏极之间的栅极。

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