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81. 发明授权

US06009205A Compressed image decompressing device 失效
标题翻译：压缩图像解压缩装置
公开(公告)号：US06009205A
公开(公告)日：1999-12-28
申请号：US611051
申请日：1996-03-05
申请人： Toyohiko Yoshida
发明人： Toyohiko Yoshida
IPC分类号： H04N19/00 , G06T9/00 , H03M7/40 , H04N1/41 , H04N19/42 , H04N19/423 , H04N19/503 , H04N19/61 , H04N19/625 , H04N19/91 , G06K9/36
CPC分类号： G06T9/007
摘要： An image processing device which processes a portion of the decompression process including a lot of comparatively complex operations like an inverse discrete cosine transform by software with using a high-performance, general-purpose processor capable of parallel processing, and the other portion of the decompression process which is comparatively simple but requires frequent access to a memory, e.g., when other frame data is to be read out for processing of encoded interframe predictive image data, or is comparatively simple but substantially hard to process in parallel, e.g., when variable length coded pixel values are to be decoded, by hardware with the use of a specialized peripheral circuit.
摘要翻译：一种图像处理装置，其通过使用能够并行处理的高性能通用处理器，以及解压缩的另一部分来处理包括大量比较复杂的操作的部分解压缩处理，如通过软件的逆离散余弦变换过程比较简单，但需要频繁访问存储器，例如当要读取其他帧数据以处理编码帧间预测图像数据时，或者比较简单但是基本上难以并行处理，例如当可变长度编码像素值将通过使用专用外围电路的硬件进行解码。

82. 发明授权

US5996070A Microprocessor capable of executing condition execution instructions using encoded condition execution field in the instructions 失效
标题翻译：能够在指令中使用编码条件执行字段执行条件执行指令的微处理器
公开(公告)号：US5996070A
公开(公告)日：1999-11-30
申请号：US783445
申请日：1997-01-16
申请人： Akira Yamada , Toyohiko Yoshida , Toru Kengaku
发明人： Akira Yamada , Toyohiko Yoshida , Toru Kengaku
IPC分类号： G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30094 , G06F9/30058 , G06F9/30072
摘要： A 3-bit condition execution field in an condition execution instruction stores an encoded value obtained by encoding a condition stored in an general purpose flag indicating to execute the condition execution instruction. A microprocessor has an instruction decode unit 2 comprising a condition execution decode section 401 for decoding a value in the condition execution field and a condition execution judgement section 402 for judging whether or not the decoded result from the condition execution decode section 401 is equal to a condition stored in general purpose flags, and outputting the indication to execute the condition execution instruction when both are equal.
摘要翻译：条件执行指令中的3位条件执行字段存储通过编码存储在指示执行条件执行指令的通用标志中的条件而获得的编码值。微处理器具有指令解码单元2，其包括用于解码条件执行区域中的值的条件执行解码单元401和条件执行判断单元402，判定来自条件执行解码单元401的解码结果是否等于条件存储在通用标志中，并且当两者相等时，输出指示以执行条件执行指令。

83. 发明授权

US5991902A Memory apparatus and data processor using the same 失效
公开(公告)号：US5991902A
公开(公告)日：1999-11-23
申请号：US812464
申请日：1997-03-06
申请人： Toyohiko Yoshida
发明人： Toyohiko Yoshida
IPC分类号： G06F12/16 , G06F11/20 , G06F12/08 , G11C29/00 , G11C29/04 , G11C29/24 , H01L27/10
CPC分类号： G11C29/24 , G11C29/70
摘要： A memory apparatus and a data processor using the same comprises, a memory mechanism, having a signal input terminal into which a predetermined signal is inputted, a memory unit consisting of first, second and third memories, a fourth memory and a control unit which replaces the first or second memory with the third memory by switching electrical connections between the memories of the memory unit according to information written into the fourth memory, and furthermore, an operation unit which diagnoses failures in the memory mechanism in case the predetermined signal is inputted from the signal input terminal, in case the failure is diagnosed in the first memory allows the control unit to replace the first memory with the third memory by writing a first value into the fourth memory, and in case the failure is diagnosed in the second memory allows the control unit to replace the second memory with the third memory by writing a second value into the fourth memory. Since the failure in the memory array unit can be relieved, manufacturing yields of the memory apparatus and the data processor including the same are improved.

84. 发明授权

US5941984A Data processing device 失效
标题翻译：数据处理装置
公开(公告)号：US5941984A
公开(公告)日：1999-08-24
申请号：US857461
申请日：1997-05-16
申请人： Atsushi Mohri , Akira Yamada , Toyohiko Yoshida
发明人： Atsushi Mohri , Akira Yamada , Toyohiko Yoshida
IPC分类号： G06F9/38 , G06F15/16
CPC分类号： G06F9/3828 , G06F9/3889
摘要： A VLIW microprocessor in which bypaths for transferring data among pipelines are incorporated between a plurality of execution units such as a memory access unit and an integer operation unit. The data on the bypaths is directly transferred to target units according to a control signal generated by a bypath processing control circuit.
摘要翻译：一种VLIW微处理器，其中用于在管线之间传送数据的逐行路径被并入在诸如存储器存取单元和整数运算单元的多个执行单元之间。根据由路径处理控制电路产生的控制信号，将路径上的数据直接传送到目标单元。

85. 发明授权

US5761470A Data processor having an instruction decoder and a plurality of executing units for performing a plurality of operations in parallel 失效
标题翻译：数据处理器具有指令解码器和用于并行执行多个操作的多个执行单元
公开(公告)号：US5761470A
公开(公告)日：1998-06-02
申请号：US574283
申请日：1995-12-18
申请人： Toyohiko Yoshida
发明人： Toyohiko Yoshida
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/3842 , G06F9/3853 , G06F9/3885
摘要： In a data processor, using a format field which specifies the number of operation fields of an instruction code and all order of execution of operations, the number of operations and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced, and decoders operate in parallel each decoding only one operation having a specific function which has a dependency on an operation execution mechanism, so that the operation fields of the instruction code are decoded in parallel by a number of decoders. While the data processor is basically a VLIW type data processor, more types of operations can be specified by the operation fields, and coding efficiency of instructions is improved since the number of operation fields and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced by means of the format field which specifies the number of the operation and the order of the operation executions.
摘要翻译：在数据处理器中，使用指定指令代码的操作字段的数量的格式字段和操作的所有执行顺序，灵活地控制操作次数和操作执行次序，并且减少空操作的必要性并且解码器并行操作，每个仅解码具有与操作执行机构相关的特定功能的一个操作，使得指令代码的操作字段由多个解码器并行解码。虽然数据处理器基本上是一个VLIW型数据处理器，但操作领域可以指定更多类型的操作，并且由于操作字段的数量和操作执行的顺序被灵活地控制，并且必须通过指定操作次数和操作执行顺序的格式字段来减少空操作。

86. 发明授权

US5745723A Data processing system capable of execution of plural instructions in parallel 失效
公开(公告)号：US5745723A
公开(公告)日：1998-04-28
申请号：US721305
申请日：1996-09-26
申请人： Masahito Matsuo , Toru Shimizu , Toyohiko Yoshida
发明人： Masahito Matsuo , Toru Shimizu , Toyohiko Yoshida
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38 , G06F11/36
CPC分类号： G06F9/3865 , G06F11/3648 , G06F9/3001 , G06F9/30149 , G06F9/3822 , G06F9/3836 , G06F9/3838 , G06F9/3869 , G06F9/3875
摘要： A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test, so that a plurality of instructions are executed in parallel with simple control.

87. 发明授权

US5560036A Data processing having incircuit emulation function 失效
标题翻译：数据处理具有电路仿真功能
公开(公告)号：US5560036A
公开(公告)日：1996-09-24
申请号：US432316
申请日：1995-05-01
申请人： Toyohiko Yoshida
发明人： Toyohiko Yoshida
IPC分类号： G06F12/08 , G06F11/26 , G06F11/28 , G06F11/36 , G06F15/78 , G06F1/00
CPC分类号： G06F11/261 , G06F11/3636 , G06F11/3648 , G06F12/0802 , G06F2212/2515
摘要： An improved data processor includes a high-speed memory that functions as a data cache during normal operation and as a trace memory to debug software in an in-circuit emulation mode. A register counts the number of storage location and overflows when a predetermined number is exceeded to cause an exception which transfers information off-chip from the trace memory. In one embodiment a starting address is stored and compared to a program counter of an instruction completely executed in the execution unit to begin the tracing.
摘要翻译：改进的数据处理器包括在正常操作期间用作数据高速缓存的高速存储器和用于以在线仿真模式调试软件的跟踪存储器。当超过预定数量时，寄存器计数存储位置的数量和溢出，从而导致从跟踪存储器转移芯片外的信息的异常。在一个实施例中，存储起始地址并将其与在执行单元中完全执行的指令的程序计数器进行比较，以开始跟踪。

88. 发明授权

US5502827A Pipelined data processor for floating point and integer operation with exception handling 失效
标题翻译：流水线数据处理器，用于具有异常处理的浮点和整数运算
公开(公告)号：US5502827A
公开(公告)日：1996-03-26
申请号：US439716
申请日：1995-05-12
申请人： Toyohiko Yoshida
发明人： Toyohiko Yoshida
IPC分类号： G06F9/38 , G06F7/00 , G06F9/46 , G06F9/48
CPC分类号： G06F9/3865
摘要： A data processor which is capable of executing two kinds of instructions, such as an integer operation instruction and a floating-point operation instruction, and which has bits in a PSW to control the timing of accepting an exception (FPU exception) generated when either of the instructions, such as the floating-point operation instruction, was executed, and which switches a mode that the FPU exception is either accepted at every end of the instructions or delayed until before execution of the following floating-point operation instruction, and which saves instruction addresses, operands, and the like related to the exception so as to perform effective processing of the FPU exception.
摘要翻译：一种数据处理器，其能够执行诸如整数运算指令和浮点运算指令的两种指令，并且在PSW中具有位以控制接收当任何一个中产生的异常（FPU异常）的定时执行诸如浮点操作指令的指令，并且切换在指令的每一端接受FPU异常的模式或者延迟到执行下一个浮点操作指令之前，并且保存与异常有关的指令地址，操作数等进行FPU异常的有效处理。

89. 发明授权

US5481734A Data processor having 2n bits width data bus for context switching function 失效
标题翻译：数据处理器具有2n位宽数据总线，用于上下文切换功能
公开(公告)号：US5481734A
公开(公告)日：1996-01-02
申请号：US627066
申请日：1990-12-13
申请人： Toyohiko Yoshida
发明人： Toyohiko Yoshida
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/38 , G06F9/46 , G06F9/48 , G06F9/00 , G06F13/00 , G06F13/40
CPC分类号： G06F9/30043 , G06F9/30036 , G06F9/30076 , G06F9/30101 , G06F9/30112 , G06F9/30149 , G06F9/34 , G06F9/3816 , G06F9/3824 , G06F9/3867 , G06F9/461
摘要： A data processor being provided with a data register having a double width of the width of a general purpose register for inputting/outputting data with respect to the operand access unit, and a data transfer path which is composed of a plurality of buses between the register file and the data register and which simultaneously transfers two data, in which, in the case where an LDCTX instruction which is the instruction for loading data to more than two register is executed, a combined data of two data each of which is to be loaded in different register is transferred from the operand access unit to the data register, and high order 4 bytes of data and low order 4 bytes of in the data register are simultaneously transfers to two register through two data transfer paths, respectively, and in the case where an STCTX instruction which is the instruction for storing data from more than two register is executed, contents of the two registers are simultaneously transferred to a high order 4 bytes and a low order 4 bytes of the data register, respectively, and two data are combined into one data in the data register, thereafter the combined data is transferred to the operand access unit in one memory accessing.
摘要翻译：数据处理器具有数据寄存器，该数据寄存器具有用于相对于操作数存取单元输入/输出数据的通用寄存器的宽度的双倍宽度，以及数据传送路径，其由寄存器之间的多条总线组成文件和数据寄存器，并且同时传送两个数据，其中在作为用于将数据加载到两个以上寄存器的指令的LDCTX指令被执行的情况下，将要加载两个数据的组合数据在不同的寄存器中从操作数存取单元传送到数据寄存器，数据寄存器中的高位4字节数据和低位4字节分别通过两条数据传输路径同时传送到两个寄存器，在这种情况下其中执行作为用于存储来自两个以上寄存器的数据的指令的STCTX指令，两个寄存器的内容被同时传送到高位4b ytes和数据寄存器的低位4字节，并且两个数据组合成数据寄存器中的一个数据，之后组合数据在一个存储器访问中被传送到操作数存取单元。

90. 发明授权

US5461715A Data processor capable of execution of plural instructions in parallel 失效
标题翻译：能够并行执行多个指令的数据处理器
公开(公告)号：US5461715A
公开(公告)日：1995-10-24
申请号：US64727
申请日：1993-05-19
申请人： Masahito Matsuo , Toru Shimizu , Toyohiko Yoshida
发明人： Masahito Matsuo , Toru Shimizu , Toyohiko Yoshida
IPC分类号： G06F9/38 , G06F9/30 , G06F9/302 , G06F11/36
CPC分类号： G06F9/3001 , G06F11/3648 , G06F9/30149 , G06F9/3816 , G06F9/3822 , G06F9/3865 , G06F9/3869 , G06F9/3875
摘要： A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test so that a plurality of instructions are executed in parallel with simple control.
摘要翻译：一种数据处理系统，能够通过与执行指令的情况相同的处理从异常处理中正确地返回，即使在指令处理的中途发生异常，也无需特别的控制，能够选择模式用于在调试或测试中逐个执行指令，使得与简单控制并行地执行多个指令。

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