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81. 发明申请

US20070184600A1 Stressed-channel CMOS transistors 审中-公开
标题翻译：高通道CMOS晶体管
公开(公告)号：US20070184600A1
公开(公告)日：2007-08-09
申请号：US11348034
申请日：2006-02-06
申请人： Da Zhang , Michael Mendicino , Bich-Yen Nguyen
发明人： Da Zhang , Michael Mendicino , Bich-Yen Nguyen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： Methods for forming portions of source and drain (S/D) regions of a first ensuing transistor (40) to include a semiconductor material (47) having a different composition of non-dopant elements than portions of S/D regions (35) of a second ensuing transistor (30) of opposite conductivity type are provided. The methods additionally include forming another semiconductor material (48) upon at least one set of the S/D regions of the ensuing transistors such that S/D surface layers of the ensuing transistors include substantially the same composition of non-dopant elements. A resulting semiconductor topography includes a pair of CMOS transistors (30, 40) collectively having S/D region surfaces with substantially the same composition of non-dopant elements. The S/D regions of one transistor (40) of the pair of CMOS transistors includes an underlying layer (47) having a different composition of non-dopant elements than underlying layers of the S/D regions (35) of the other transistor (30).
摘要翻译：用于形成第一随后晶体管（40）的源极和漏极（S / D）区域的部分的方法，以包括具有与S / D区域（35）的部分不同的非掺杂元素的不同组成的半导体材料（47）提供了具有相反导电类型的第二随后的晶体管（30）。所述方法还包括在随后的晶体管的至少一组S / D区上形成另一半导体材料（48），使得随后的晶体管的S / D表面层包括基本上相同的非掺杂元素组成。所得到的半导体形貌包括一对共同具有基本上相同组成的非掺杂元素的S / D区域表面的CMOS晶体管（30,40）。该对CMOS晶体管的一个晶体管（40）的S / D区域包括与另一个晶体管的S / D区域（35）的下层不同的非掺杂元素组成的下层（47） 30）。

82. 发明授权

US07226820B2 Transistor fabrication using double etch/refill process 有权
标题翻译：使用双重蚀刻/补充工艺的晶体管制造
公开(公告)号：US07226820B2
公开(公告)日：2007-06-05
申请号：US11101354
申请日：2005-04-07
申请人： Da Zhang , Jing Liu , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
发明人： Da Zhang , Jing Liu , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/00
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.
摘要翻译：半导体制造工艺包括形成覆盖在半导体衬底（102）上的栅电介质（110）上的栅电极（120）。第一间隔物（124）形成在栅电极（120）的侧壁上。使用栅电极（120）和第一间隔物（124）作为掩模，在基板（102）中形成第一s / d沟槽（130）。第一s / d沟槽（130）填充有第一s / d结构（132）。第二间隔物（140）形成在邻近第一间隔物（124）的栅电极（120）侧壁上。使用栅电极（120）和第二间隔物（140）作为掩模，在衬底（102）中形成第二s / d沟槽（150）。第二s / d沟槽（150）填充有第二s / d结构（152）。填充第一和第二s / d沟槽（130,150）优选地包括使用外延工艺来生长s / d结构。 s / d结构（132,152）可以是应力诱导结构，例如用于PMOS晶体管的硅锗和用于NMOS晶体管的硅碳。

83. 发明申请

US20070099361A1 Method for forming a semiconductor structure and structure thereof 有权
公开(公告)号：US20070099361A1
公开(公告)日：2007-05-03
申请号：US11263119
申请日：2005-10-31
申请人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam Sadaka , Da Zhang
发明人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam Sadaka , Da Zhang
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L21/845 , H01L27/1211 , H01L29/7842 , H01L29/785
摘要： Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.

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