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81. 发明授权

US06532185B2 Distribution of bank accesses in a multiple bank DRAM used as a data buffer 有权
公开(公告)号：US06532185B2
公开(公告)日：2003-03-11
申请号：US09792605
申请日：2001-02-23
申请人： Jean Louis Calvignac , Peter Irma August Barri , Ivan Oscar Clemminck , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Bart Joseph Gerard Pauwels , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Jean Louis Calvignac , Peter Irma August Barri , Ivan Oscar Clemminck , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Bart Joseph Gerard Pauwels , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： G11C800
CPC分类号： H04L49/901 , G06F12/0607 , H04L49/90 , H04L49/9031
摘要： Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.

82. 发明授权

US08195705B2 Hybrid search memory for network processor and computer systems 有权
标题翻译：用于网络处理器和计算机系统的混合搜索存储器
公开(公告)号：US08195705B2
公开(公告)日：2012-06-05
申请号：US10015165
申请日：2001-12-11
申请人： Jean Louis Calvignac , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Fabrice Jean Verplanken
IPC分类号： G06F17/30
CPC分类号： G06F17/30327
摘要： A system includes a data structure having a Direct Table (DT), Patricia-Trees, Pointers and high speed storage systems such as Contents Address Memory (CAM). The DT has a plurality of entries with each one coupled to a Patricia Tree having multiple nodes coupled to leaves. The number of Nodes, termed a threshold, that can be traversed to obtain information in the leaves is limited to a predetermined value. Once the threshold is reached a pointer indicates the address of the CAM and the address of the leaves is stored in the CAM. By using the structure and method the latency associated with tree search is significantly reduced.
摘要翻译：系统包括具有直接表（DT），帕特里夏树，指针和诸如内容地址存储器（CAM）的高速存储系统的数据结构。 DT具有多个条目，其中每个条目耦合到具有耦合到叶子的多个节点的Patricia Tree。被称为阈值的节点数量，可以被遍历以获得叶子中的信息被限制到预定值。一旦达到阈值，指针指示CAM的地址，并且叶子的地址被存储在CAM中。通过使用结构和方法，与树搜索相关联的延迟显着降低。

83. 发明授权

US07327759B2 Sequence-preserving deep-packet processing in a multiprocessor system 失效
标题翻译：在多处理器系统中对序列进行深度包处理
公开(公告)号：US07327759B2
公开(公告)日：2008-02-05
申请号：US09912781
申请日：2001-07-25
申请人： Jean Louis Calvignac , Mohammad Peyravian , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Mohammad Peyravian , Fabrice Jean Verplanken
IPC分类号： H04J3/24
CPC分类号： H04L49/9094 , H04L47/10 , H04L47/34 , H04L49/90 , H04L49/9089
摘要： Packets or frames of data may be compressed, encrypted/decrypted, filtered, classified, searched or subjected to other deep-packet processing operations before being distributed through the internet. The microprocessor system and method of the present invention provide for the orderly processing of such data packets without disrupting or changing the sequence in which the data is intended to be transmitted to its destination. This is achieved by receiving frames into an input buffer for processing. Associated with this input buffer is a unit for determining the operation to be performed on each frame. An arbitrator assigns each frame to a processing core engine. An output buffer collects the processed frames, and a sequencer forwards the processed frames from the output buffer to their destination in the same order as received by the input/output buffer. Maintaining the sequence of data transmission is particularly useful in voice transmission, such as videos and movies.
摘要翻译：数据包或数据帧可以在通过因特网分发之前被压缩，加密/解密，过滤，分类，搜索或经受其他深度包处理操作。本发明的微处理器系统和方法提供这种数据分组的有序处理，而不会中断或改变数据要发送到其目的地的序列。这通过将帧接收到用于处理的输入缓冲器中来实现。与该输入缓冲器相关联的是用于确定要在每个帧上执行的操作的单元。仲裁员将每个帧分配给处理核心引擎。输出缓冲器收集经处理的帧，并且定序器按照输入/输出缓冲器接收的顺序将处理后的帧从输出缓冲区转发到其目的地。保持数据传输的顺序在诸如视频和电影的语音传输中特别有用。

84. 发明授权

US07315901B1 Method and system for network processor scheduling outputs using disconnect/reconnect flow queues 失效
标题翻译：使用断开/重新连接流队列的网络处理器调度输出的方法和系统
公开(公告)号：US07315901B1
公开(公告)日：2008-01-01
申请号：US09548913
申请日：2000-04-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F15/173 , H04L12/24
CPC分类号： H04L47/522 , H04L47/2425 , H04L47/50 , H04L47/568 , H04L47/58 , H04L47/6235 , H04L47/6265
摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. A system for allowing peak bursts based on a system of credits and charges is taught along limits on such peak bursts. Also taught is a system for preventing a flow's disconnection and reconnection to the queues from allowing it to unfairly achieve an improved position.
摘要翻译：一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。根据这种峰值突发的限制，教导了基于信用和费用系统允许峰值突发的系统。还教导了一种用于防止流动断开和重新连接到队列的系统，从而允许其不公平地实现改进的位置。

85. 发明授权

US07133931B1 Method and system for making a frame alteration in a network processing system 失效
标题翻译：在网络处理系统中进行帧改变的方法和系统
公开(公告)号：US07133931B1
公开(公告)日：2006-11-07
申请号：US09479026
申请日：2000-01-07
申请人： Samuel Steven Allison , Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Samuel Steven Allison , Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F15/16 , G06F15/167 , H04B7/216 , H04L12/28
CPC分类号： H04L49/30 , H04L49/109
摘要： A system and method of altering frames being processed by a network processing unit. The system includes a set of defined alterations, with some of the alterations being fixed alterations which are advantageously handled by hardware to accomplish the fixed alterations rapidly and without executing a stored program and other alterations which include a variable portion, with these variable alterations being accomplished through the use of stored programs allowing the variables to be used to effect variable alterations to a frame. The present system accommodates a change in the duration of life of a frame or information unit and addition or deletion of bits and also allows for a new cyclic redundancy checking to be accomplished for a revised information unit. Advantageously, the frame alteration system is on the same substrate as the processors.
摘要翻译：一种改变由网络处理单元处理的帧的系统和方法。该系统包括一组定义的改变，其中一些变化是固定的改变，其有利地被硬件处理以快速完成固定的变更，而不执行存储的程序和包括可变部分的其他改变，这些可变改变被完成通过使用存储的程序，允许使用变量来实现对框架的变化。本系统适应帧或信息单元的持续时间的改变以及比特的添加或删除，并且还允许为修改的信息单元完成新的循环冗余校验。有利地，框架改变系统在与处理器相同的衬底上。

86. 发明授权

US07120630B2 Full match (FM) search algorithm implementation for a network processor 失效
标题翻译：网络处理器的完全匹配（FM）搜索算法实现
公开(公告)号：US07120630B2
公开(公告)日：2006-10-10
申请号：US10650397
申请日：2003-08-28
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F7/00 , H04L12/56
CPC分类号： H04L45/742 , H04L45/7453 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key.
摘要翻译：用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。检索所需的两个密钥和相应的信息都存储在Patricia树结构中。散列函数提供密钥的比特到散列密钥的比特的n> n映射。

87. 发明授权

US06987760B2 High speed network processor 有权
公开(公告)号：US06987760B2
公开(公告)日：2006-01-17
申请号：US09838395
申请日：2001-04-19
申请人： Jean Louis Calvignac , William John Goetzinger , Glen Howard Handlogten , Marco C. Heddes , Joseph Franklin Logan , James Francis Mikos , David Alan Norgaard , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , William John Goetzinger , Glen Howard Handlogten , Marco C. Heddes , Joseph Franklin Logan , James Francis Mikos , David Alan Norgaard , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L2012/5636 , H04L2012/5679 , H04L2012/5685
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.

88. 发明授权

US06977928B1 Method and system for data flow multicasting 有权
标题翻译：数据流多播的方法和系统
公开(公告)号：US06977928B1
公开(公告)日：2005-12-20
申请号：US09548906
申请日：2000-04-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L12/18 , H04L12/28
CPC分类号： H04L12/18
摘要： A system and method of transmitting multiple output messages from a single input message system where the system is keeping the messages in order by correlating the output messages with the input messages. For each output message, an indicator is associated with the output message indicating whether this output message is the last message being generated for the given input message. This allows multicasting to occur in a system where the output is matched to the input by allowing multiple output messages to be associated with a single input message.
摘要翻译：从单个输入消息系统发送多个输出消息的系统和方法，其中系统通过将输出消息与输入消息相关联来保持消息的顺序。对于每个输出消息，指示符与输出消息相关联，指示该输出消息是否是针对给定输入消息生成的最后消息。这允许在通过允许多个输出消息与单个输入消息相关联的输出与输入匹配的系统中发生多播。

89. 发明授权

US06681340B2 Efficient implementation of error correction code scheme 失效
标题翻译：有效执行纠错码方案
公开(公告)号：US06681340B2
公开(公告)日：2004-01-20
申请号：US09792533
申请日：2001-02-23
申请人： Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F1110
CPC分类号： H04L1/0043 , H04L1/0063
摘要： A method and system for efficiently implementing an error correction code scheme. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. Each frame of data may be associated with a frame control block. The processor comprises a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor further comprises a second queue configured to store one or more frame control blocks not associated with a frame of data. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity bit. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme.
摘要翻译：一种用于有效实施纠错码方案的方法和系统。在本发明的一个实施例中，系统包括被配置为处理数据帧的处理器。数据帧可以与帧控制块相关联。处理器包括被配置为存储与一个或多个数据帧相关联的一个或多个帧控制块的第一队列。处理器还包括被配置为存储与数据帧不相关联的一个或多个帧控制块的第二队列。与第一队列中的一个或多个数据帧相关联的一个或多个帧控制块包括用于存储奇偶校验位的位。第二队列中的一个或多个帧控制块包括用于存储纠错码方案的代码的多个比特。

90. 发明授权

US06671280B1 Network processor for multiprotocol data flows 有权
标题翻译：用于多协议数据流的网络处理器
公开(公告)号：US06671280B1
公开(公告)日：2003-12-30
申请号：US09535794
申请日：2000-03-29
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L1256
CPC分类号： H04L49/30 , H04L45/502 , H04L49/201 , H04L49/251 , H04L49/3009 , H04L49/602 , H04L49/606 , H04L2012/5618 , H04L2012/5665
摘要： A method for integrating Asynchronous Transfer Mode (ATM) and frame-based traffic flows within a telecommunications network is disclosed. The telecommunications network includes a network processor having upside processing means for delivering an incoming flow from the telecommunications network to a switch and downside processing means for delivering outgoing network traffic from the switch to the telecommunications network. The incoming flow is initially received at the upside processing means as a frame-based flow. The incoming flow may be characterized as belonging to a group having frame-based flows and ATM flows. In response to the receipt of the incoming flow, the incoming flow is determined if it is destined for a legacy, ATM-only device. The incoming flow is then processed according to the determined routing requirements and the incoming flow characterization before delivering the incoming flow to the switch.
摘要翻译：公开了一种在电信网络内集成异步传输模式（ATM）和基于帧的业务流的方法。电信网络包括具有上行处理装置的网络处理器，用于将来自电信网络的输入流传送到交换机，以及下行处理装置，用于将来自交换机的输出网络业务传送到电信网络。最初在上行处理装置处接收输入流作为基于帧的流。输入流可以被表征为属于具有基于帧的流和ATM流的组。响应于接收到的流入，确定进入流是否发往传统的仅ATM设备。然后根据确定的路由要求和输入流特性，将传入流量传送到交换机之前处理进入流。

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