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81. 发明授权

US07375854B2 Method for color correction 失效
标题翻译：颜色校正方法
公开(公告)号：US07375854B2
公开(公告)日：2008-05-20
申请号：US10798867
申请日：2004-03-12
申请人： Ching-Hsiang Hsu , Yuh-Ren Shen , Ling-Chih Lu
发明人： Ching-Hsiang Hsu , Yuh-Ren Shen , Ling-Chih Lu
IPC分类号： G06F15/00 , G03F3/08 , G06K9/00
CPC分类号： H04N9/69 , H04N5/202
摘要： A method for color correction is provided. In this method, a plurality of groups of gray levels and luminance of light source of display device are respectively selected by color measurement system. The selected data of each color light are respectively calculated to obtain fitting functions which can fit the gray level data of each interval. The fitting luminance of the gray levels in interval is obtained by the fitting function and formed into a lookup table. Then in order to correspond a gamma curve of normalized gray data of image to a predetermined target curve, the two gamma curves are first taken to logarithmic calculation and the modified gray signals are obtained from the lookup table, then the modified gray signals are transmitted out for providing the display device to express the gray distribution state. The method for color correction is applicable to various display devices, especially liquid crystal display device.
摘要翻译：提供了一种用于颜色校正的方法。在该方法中，通过彩色测量系统分别选择多组灰度级和显示装置的光源亮度。分别计算每个颜色光的所选数据，以获得可以适合每个间隔的灰度级数据的拟合函数。通过拟合函数获得间隔中灰度级的拟合亮度，形成查找表。然后，为了将图像的归一化灰度数据的伽马曲线对应于预定的目标曲线，首先将两个伽马曲线进行对数计算，并从查找表中获得修改的灰度信号，然后将修改的灰度信号发送出去用于提供显示装置来表达灰色分布状态。用于颜色校正的方法适用于各种显示装置，特别是液晶显示装置。

82. 发明申请

US20080050406A1 Modified Mite Allergen and Pharmaceutical Uses Thereof 有权
标题翻译：改良螨过敏原及其制药用途
公开(公告)号：US20080050406A1
公开(公告)日：2008-02-28
申请号：US11778946
申请日：2007-07-17
申请人： Ching-Hsiang Hsu , Wei-Chih Su
发明人： Ching-Hsiang Hsu , Wei-Chih Su
IPC分类号： A61K39/35 , A61P37/00
CPC分类号： A61K39/35 , C07H21/04 , C07K14/43531 , Y10S530/868
摘要： The present invention provides a modified Dermatophagoides pteronyssinus allergen Der p 5 protein which has ability to inhibit IgE binding when exposed against to the antigen. A method for treating allergy comprising administrating a therapeutically effective dose of the modified D. pteronyssinus allergen Der p 5 protein to a subject suffering from allergy Der p 5 is also provided.
摘要翻译：本发明提供了当暴露于抗原时具有抑制IgE结合的能力的修饰的Dermatophagoides pteronyssinus变应原Der p 5蛋白。还提供了治疗过敏的方法，其包括将治疗有效剂量的经修饰的D.tteronyssinus变应原Der p 5蛋白施用于患有过敏Der p 5的受试者。

83. 发明申请

US20050201615A1 Method for color correction 失效
标题翻译：颜色校正方法
公开(公告)号：US20050201615A1
公开(公告)日：2005-09-15
申请号：US10798867
申请日：2004-03-12
申请人： Ching-Hsiang Hsu , Yuh-Ren Shen , Ling-Chih Lu
发明人： Ching-Hsiang Hsu , Yuh-Ren Shen , Ling-Chih Lu
IPC分类号： G06K1/00 , G06K9/00
CPC分类号： H04N9/69 , H04N5/202
摘要： A method for color correction is provided. In this method, a plurality of groups of gray levels and luminance of light source of display device are respectively selected by color measurement system. The selected data of each color light are respectively calculated to obtain fitting functions which can fit the gray level data of each interval. The fitting luminance of the gray levels in interval is obtained by the fitting function and formed into a lookup table. Then in order to correspond a gamma curve of normalized gray data of image to a predetermined target curve, the two gamma curves are first taken to logarithmic calculation and the modified gray signals are obtained from the lookup table, then the modified gray signals are transmitted out for providing the display device to express the gray distribution state. The method for color correction is applicable to various display devices, especially liquid crystal display device.
摘要翻译：提供了一种用于颜色校正的方法。在该方法中，通过彩色测量系统分别选择多组灰度级和显示装置的光源亮度。分别计算每个颜色光的所选数据，以获得可以适合每个间隔的灰度级数据的拟合函数。通过拟合函数获得间隔中灰度级的拟合亮度，形成查找表。然后，为了将图像的归一化灰度数据的伽马曲线对应于预定的目标曲线，首先将两个伽马曲线进行对数计算，并从查找表中获得修改的灰度信号，然后将修改的灰度信号发送出去用于提供显示装置来表达灰色分布状态。用于颜色校正的方法适用于各种显示装置，特别是液晶显示装置。

84. 发明申请

US20050186189A1 Novel microorganism strain GM-020 of Lactobacillus rhamnosus and its use for treating obesity 审中-公开
标题翻译：鼠李糖杆菌的新型微生物菌株GM-020及其用于治疗肥胖症的用途
公开(公告)号：US20050186189A1
公开(公告)日：2005-08-25
申请号：US10956138
申请日：2004-10-04
申请人： Ching-Hsiang Hsu , Wei-Chih Su
发明人： Ching-Hsiang Hsu , Wei-Chih Su
IPC分类号： A61K35/74 , A61K35/747 , A61K45/00 , C12N1/20 , C12R1/225
CPC分类号： C12R1/225 , A61K35/747 , A61K36/07 , C12N1/20 , A61K2300/00
摘要： The present invention provides an isolated microorganism strain, Lactobacillus rhamnosus GM-020, which is found to be effective in treating obesity and a complication thereof. The use of the Lactobacillus rhamnosus GM-020 in treating obesity and a complication thereof is also provided.
摘要翻译：本发明提供分离的微生物菌株，鼠李糖乳杆菌GM-020，其被发现在治疗肥胖症和其并发症中是有效的。还提供了使用鼠李糖乳杆菌GM-020治疗肥胖症及其并发症。

85. 发明申请

US20050037812A1 Island type mobile communication arrangement 有权
标题翻译：岛式移动通信安排
公开(公告)号：US20050037812A1
公开(公告)日：2005-02-17
申请号：US10714626
申请日：2003-11-18
申请人： Ching-Hsiang Hsu , Charlie Chen , Hsiao-Wei Hsu , Kan-Lin Lee
发明人： Ching-Hsiang Hsu , Charlie Chen , Hsiao-Wei Hsu , Kan-Lin Lee
IPC分类号： H04L12/28 , H04W4/04 , H04W4/20 , H04W8/06 , H04W16/00 , H04W16/20 , H04W64/00 , H04W84/02 , H04W84/10 , H04Q7/20
CPC分类号： H04W16/00 , H04W4/04 , H04W4/20 , H04W8/06 , H04W64/00 , H04W84/02 , H04W84/10
摘要： An island type mobile communication arrangement is disclosed. A plurality of BTSs connected to BSCs are reassigned as island BTSs and connected to an island BSC, the island BSC is connected to an island MSC. When entering or leaving the scope of the island MSC, a cellular phone performs a location updating procedure, and thus the island type mobile communication arrangement can provide a special service to all cellular phones in a particular local area by reading MSISDNs in an island VLR corresponding to the island MSC.
摘要翻译：公开了一种岛式移动通信装置。连接到BSC的多个BTS被重新分配为岛BTS并连接到岛BSC，岛BSC连接到岛MSC。当进入或离开岛MSC的范围时，蜂窝电话执行位置更新过程，因此岛式移动通信装置可以通过读取对应的岛屿VLR中的MSISDN来向特定局部区域中的所有蜂窝电话提供特殊服务到海岛MSC。

86. 发明授权

US06735115B2 Nonvolatile semiconductor memory device having divided bit lines 失效
标题翻译：具有划分位线的非易失性半导体存储器件
公开(公告)号：US06735115B2
公开(公告)日：2004-05-11
申请号：US09956212
申请日：2001-09-18
申请人： Ching-Hsiang Hsu , Ching-Song Yang
发明人： Ching-Hsiang Hsu , Ching-Song Yang
IPC分类号： G11C1604
CPC分类号： G11C16/24
摘要： A non-volatile semiconductor memory device having divided bit lines. A main bit line is controlled by at least one bit line selection device to transfer its potential to a selected sub bit line, such that memory cells in a selected sector work and overloading of the bit line generated by a parasitic capacitance can be prevented. The memory cells and the bit line selection device are arranged in parallel in a P-well and a N-well, respectively, thereby preventing disturbances during programming or erasing the bit line.
摘要翻译：具有划分位线的非易失性半导体存储器件。主位线由至少一个位线选择装置控制，以将其电位转移到所选择的子位线，使得可以防止所选扇区中的存储器单元工作，并且可以防止由寄生电容产生的位线的过载。存储单元和位线选择装置分别并排布置在P阱和N阱中，从而防止在编程或擦除位线期间的干扰。

87. 发明授权

US06580641B2 Method of forming and operating trench split gate non-volatile flash memory cell structure 失效
公开(公告)号：US06580641B2
公开(公告)日：2003-06-17
申请号：US10065590
申请日：2002-10-31
申请人： Meng-Yi Wu , Kung-Hong Lee , Fu-Yuan Chen , Hsin-Fen Chou , Ching-Song Yang , Ya-Chin Kin , Ching-Hsiang Hsu
发明人： Meng-Yi Wu , Kung-Hong Lee , Fu-Yuan Chen , Hsin-Fen Chou , Ching-Song Yang , Ya-Chin Kin , Ching-Hsiang Hsu
IPC分类号： G11C1134
CPC分类号： H01L27/11553 , G11C16/0433 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/66825
摘要： A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.

88. 发明授权

US06566703B1 High speed flash memory with high coupling ratio 有权
标题翻译：具有高耦合比的高速闪存
公开(公告)号：US06566703B1
公开(公告)日：2003-05-20
申请号：US09665745
申请日：2000-09-20
申请人： Mong-Song Liang , Ching-Hsiang Hsu , Ruei-Ling Lin
发明人： Mong-Song Liang , Ching-Hsiang Hsu , Ruei-Ling Lin
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory device includes floating gate electrode, an interelectrode dielectric layer and a control gate electrode. The interelectrode dielectric layer is formed on top of the floating gate electrode and the control gate electrode is formed on top of the interelectrode dielectric layer. A doped silicon semiconductor substrate is covered with variable thickness silicon oxide regions on the surface thereof with junctions between the variable thickness regions. The silicon oxide regions are substantially thicker beneath the center of the floating gate electrode. Source/drain regions formed in the substrate extend beneath the tunnel oxide regions with the junctions aligned with the regions. The floating gate electrodes formed over the silicon oxide regions above the source/drain regions including dielectric sidewalls within the floating gate electrode above the junctions. The variable thickness silicon oxide regions are tunnel oxide regions on either side of a gate oxide region. The floating gate electrode is composed of doped polysilicon and the dielectric sidewalls is reoxidized polysilicon dielectric regions formed within the floating gate electrode above the junctions of the tunnel oxide regions and the gate oxide region.
摘要翻译：闪存器件包括浮栅电极，电极间电介质层和控制栅电极。电极间电介质层形成在浮栅电极的顶部，并且控制栅电极形成在电极间电介质层的顶部。掺杂硅半导体衬底在其表面上被可变厚度的氧化硅区域覆盖，其中可变厚度区域之间具有接合点。氧化硅区域在浮栅电极的中心下方基本上更厚。形成在衬底中的源极/漏极区域在隧道氧化物区域的下方延伸，并且结点与区域对准。形成在源极/漏极区域之上的氧化硅区域上方的浮置栅电极，包括位于结点之上的浮动栅电极内的电介质侧壁。可变厚度的氧化硅区域是栅极氧化物区域两侧的隧道氧化物区域。浮置栅电极由掺杂的多晶硅组成，电介质侧壁是形成在隧道氧化物区域和栅极氧化物区域的结点之上的浮置栅电极内的再氧化的多晶硅介质区域。

89. 发明授权

US06448607B1 Nonvolatile memory having embedded word lines 有权
标题翻译：具有嵌入字线的非易失性存储器
公开(公告)号：US06448607B1
公开(公告)日：2002-09-10
申请号：US09683212
申请日：2001-12-03
申请人： Ching-Hsiang Hsu , Kung-Hong Lee , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Kung-Hong Lee , Ching-Sung Yang
IPC分类号： H01L29788
CPC分类号： H01L29/42336 , G11C8/14 , G11C11/5671 , G11C16/0475 , G11C16/08 , H01L27/115 , H01L29/7883
摘要： A flash memory cell with an embedded gate structure capable of storing two bits of information and the operation of such a flash memory cell are provided. A first ion-doped region, serving as a source terminal, is formed in a semiconductor substrate. An embedded gate structure and a second ion-doped region are alternately arranged on the first ion-doped region. The embedded gate structure is surrounded by the first oxide layer, the trapping layer, and the second oxide layer. An insulating layer is formed on the embedded gate structure. A diffusion drain is positioned atop the second ion-doped region and a conductive layer connects with the diffusion drains. The embedded gate structure is isolated from the diffusion drain with the insulating layer. Furthermore, the reading, programming, and erasing operation of the memory cell with two bits of information are provided.
摘要翻译：提供具有能够存储两位信息的嵌入式门结构和这种闪存单元的操作的闪存单元。作为源极端子的第一离子掺杂区域形成在半导体衬底中。嵌入栅极结构和第二离子掺杂区域交替地布置在第一离子掺杂区域上。嵌入式栅极结构被第一氧化物层，俘获层和第二氧化物层包围。在嵌入式栅极结构上形成绝缘层。扩散漏极位于第二离子掺杂区域顶部，导电层与扩散漏极连接。嵌入式栅极结构与绝缘层与扩散漏极隔离。此外，提供了具有两位信息的存储单元的读取，编程和擦除操作。

90. 发明授权

US06281545B1 Multi-level, split-gate, flash memory cell 有权
标题翻译：多级，分闸，闪存单元
公开(公告)号：US06281545B1
公开(公告)日：2001-08-28
申请号：US09199130
申请日：1998-11-24
申请人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
发明人： Mong-Song Liang , Di-Son Kuo , Ching-Hsiang Hsu , Ruei-Ling Lin
IPC分类号： H01L29788
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , G11C2211/5612 , H01L21/28273 , H01L29/66825 , H01L29/7887
摘要： A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes. There are source/drain regions in the substrate self-aligned with the control gate electrode.
摘要翻译：半导体存储器件形成在掺杂半导体衬底上，并被掺杂的第一多晶硅层依次覆盖的隧道氧化物层覆盖。将第一多晶硅层图案化成一对浮栅电极。电极间电介质层覆盖浮置栅电极，浮置栅电极的侧壁和隧道氧化物的边缘在浮栅电极下方。第二多晶硅层覆盖在电极之间的电介质层上，又由硅化钨层覆盖。第二介电层覆盖硅化钨层。跨越一对浮置栅电极的控制栅极电极由第二多晶硅层形成，硅化钨和第一和第二电介质层图案化成栅电极堆叠，提供横跨该对浮置栅电极的控制栅电极。衬底中的源极/漏极区域与控制栅电极自对准。

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