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    • 84. 发明申请
    • MANUFACTURING AND CLEANSING OF THIN FILM TRANSISTOR PANELS
    • 薄膜晶体管面板的制造和清洁
    • US20100099595A1
    • 2010-04-22
    • US12645471
    • 2009-12-22
    • Hong-Sick Park
    • Hong-Sick Park
    • C11D7/32
    • C11D11/0047C11D7/263C11D7/3281
    • A manufacturing a thin film transistor array panel includes depositing a first thin film including aluminum on a substrate, patterning the first thin film by photolithography and etching, cleansing the substrate including the first thin film, and depositing a second thin film on the cleansed substrate. The cleansing is performed using a cleansing material including ultrapure water, cyclic amine, pyrogallol, benzotrizole, and methyl glycol. The cleansing material includes ultrapure water at about 85 wt % to about 99 wt %, cyclic amine at about 0.01 wt % to about 1.0 wt %, pyrogallol at about 0.01 wt % to 1.0 wt %, benzotrizole at about 0.01 wt % to 1.0 wt %, and methyl glycol at about 0.01 wt % to 1.0 wt %.
    • 制造薄膜晶体管阵列面板包括在基板上沉积包括铝的第一薄膜,通过光刻和蚀刻对第一薄膜进行图案化,清洗包括第一薄膜的基板,以及在清洁的基板上沉积第二薄膜。 使用包括超纯水,环胺,连苯三酚,苯并三唑和甲基二醇的清洁材料进行清洁。 清洁材料包括约85重量%至约99重量%的超纯水,约0.01重量%至约1.0重量%的环胺,约0.01重量%至1.0重量%的连苯三酚,约0.01重量%至1.0重量%的苯并三唑 %和约0.01重量%至1.0重量%的甲基二醇。
    • 85. 发明授权
    • Signal line for display device and thin film transistor array panel including the signal line
    • 信号线用于显示器件和薄膜晶体管阵列面板,包括信号线
    • US07462895B2
    • 2008-12-09
    • US11296603
    • 2005-12-06
    • Hong-Sick ParkShi-Yul Kim
    • Hong-Sick ParkShi-Yul Kim
    • H01L29/10
    • H01L29/4908H01L27/12H01L27/124H01L29/458
    • A thin film transistor (TFT) array panel with signal lines that have low resistivity is presented. The TFT array panel includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer formed on the gate line, a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode facing the source electrode with a gap, and a pixel electrode connected to the drain electrode. In one embodiment, at least one of the gate line, the data line, and the drain electrode includes a first conductive layer made of a Mo-containing conductor, a second conductive layer made of a Cu-containing conductor, and a third conductive layer made of a MoN-containing conductor.
    • 提出了具有低电阻率的信号线的薄膜晶体管(TFT)阵列面板。 TFT阵列面板包括绝缘基板,形成在绝缘基板上的栅极线,形成在栅极线上的栅极绝缘层,漏极电极和形成在栅极绝缘层上的源电极的数据线, 具有间隙的源电极和连接到漏电极的像素电极。 在一个实施例中,栅极线,数据线和漏电极中的至少一个包括由含Mo导体制成的第一导电层,由含Cu导体制成的第二导电层和第三导电层 由含MoN的导体制成。
    • 86. 发明申请
    • METHOD FOR MANUFACTURING A SIGNAL LINE, THIN FILM TRANSISTOR PANEL, AND METHOD FOR MANUFACTURING THE THIN FILM TRANSISTOR PANEL
    • 用于制造信号线,薄膜晶体管板的方法和制造薄膜晶体管板的方法
    • US20080203390A1
    • 2008-08-28
    • US11932233
    • 2007-10-31
    • Do-Hyun KimWon-Suk ShinChang-Oh JeongHong-Sick ParkEun-Guk LeeJe-Hun Lee
    • Do-Hyun KimWon-Suk ShinChang-Oh JeongHong-Sick ParkEun-Guk LeeJe-Hun Lee
    • H01L29/49H01L21/44H01L21/84
    • H01L27/12H01L27/124H01L27/1288H01L29/458
    • A method for manufacturing a thin film transistor array panel includes forming a gate line on a substrate; sequentially forming a gate insulating layer, a silicon layer, and a conductor layer including a lower layer and an upper layer on the gate line, forming a photoresist film, on the conductor layer, patterning the photoresist film to form a photoresist pattern including a first portion and a second portion having a greater thickness than the first portion, etching the upper layer and the lower layer by using the photoresist pattern as art etch mask, etching the silicon layer by using the photoresist pattern as an etch mask to form a semiconductor, removing the second portion of the photoresist pattern by using an etch back process, selectively wet-etching the upper layer of the conductor layer by using the photoresist pattern as an etch mask, dry-etching the lower layer of the conductor layer by using the photoresist pattern as an etch mask to form a data line and a drain electrode including remaining upper and lower layers, and forming a pixel electrode connected to the drain electrode.
    • 一种制造薄膜晶体管阵列面板的方法,包括在基板上形成栅极线; 在栅极线上顺序地形成栅极绝缘层,硅层和包括下层和上层的导体层,在导体层上形成光致抗蚀剂膜,图案化光致抗蚀剂膜以形成包括第一 部分和第二部分具有比第一部分更大的厚度,通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻上层和下层,通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻硅层以形成半导体, 通过使用回蚀工艺去除光致抗蚀剂图案的第二部分,通过使用光致抗蚀剂图案作为蚀刻掩模来选择性地湿法蚀刻导体层的上层,通过使用光致抗蚀剂干蚀刻导体层的下层 图案作为蚀刻掩模以形成包括剩余的上层和下层的数据线和漏极,并且形成连接到漏电极的像素电极 。
    • 88. 发明申请
    • Manufacturing and cleansing of thin film transistor panels
    • 制造和清洗薄膜晶体管面板
    • US20070129274A1
    • 2007-06-07
    • US11636008
    • 2006-12-06
    • Hong-Sick Park
    • Hong-Sick Park
    • C11D7/32
    • C11D11/0047C11D7/263C11D7/3281
    • A manufacturing a thin film transistor array panel includes depositing a first thin film including aluminum on a substrate, patterning the first thin film by photolithography and etching, cleansing the substrate including the first thin film, and depositing a second thin film on the cleansed substrate. The cleansing is performed using a cleansing material including ultrapure water, cyclic amine, pyrogallol, benzotrizole, and methyl glycol. The cleansing material includes ultrapure water at about 85 wt % to about 99 wt %, cyclic amine at about 0.01 wt % to about 1.0 wt %, pyrogallol at about 0.01 wt % to 1.0 wt %, benzotrizole at about 0.01 wt % to 1.0 wt %, and methyl glycol at about 0.01 wt % to 1.0 wt %.
    • 制造薄膜晶体管阵列面板包括在基板上沉积包括铝的第一薄膜,通过光刻和蚀刻对第一薄膜进行图案化,清洗包括第一薄膜的基板,以及在清洁的基板上沉积第二薄膜。 使用包括超纯水,环胺,连苯三酚,苯并三唑和甲基二醇的清洁材料进行清洁。 清洁材料包括约85重量%至约99重量%的超纯水,约0.01重量%至约1.0重量%的环胺,约0.01重量%至1.0重量%的连苯三酚,约0.01重量%至1.0重量%的苯并三唑 %和约0.01重量%至1.0重量%的甲基二醇。
    • 90. 发明授权
    • Etchant for wire, method of manufacturing wire using etchant, thin film transistor array panel including wire and manufacturing method thereof
    • 线蚀刻剂,使用蚀刻剂制造线的方法,包括线的薄膜晶体管阵列面板及其制造方法
    • US07141180B2
    • 2006-11-28
    • US10607316
    • 2003-06-25
    • Hong-Sick ParkSung-Chul KangHong-Je Cho
    • Hong-Sick ParkSung-Chul KangHong-Je Cho
    • C09K13/00
    • C23F1/30C09K13/06C23F1/02H01L21/32134H01L27/124H01L27/13
    • A method of manufacturing a TFT array panel according to the present invention forms a gate wire on an insulating substrate. The gate wire includes a plurality of gate lines and a plurality of gate electrodes connected to the gate lines. A semiconductor layer and a gate insulating layer are sequentially formed and a data wire is formed thereon. The data wire includes a plurality of data lines intersecting the gate lines, a plurality of source electrodes connected to the data lines and placed close to the gate electrodes, and a plurality of drain electrodes opposite the source electrodes with respect to the gate electrodes. A passivation layer is deposited and patterned to form a plurality of contact holes exposing the drain electrodes at least. A conductive layer made of Ag or Ag alloy is deposited on the passivation layer, and is patterned using an etchant containing ferric nitrate, nitric acid, acetic acid, hexamethylenetetramine and deionized water to form a plurality of reflective films electrically connected to the drain electrodes.
    • 根据本发明的TFT阵列板的制造方法在绝缘基板上形成栅极线。 栅极线包括多个栅极线和连接到栅极线的多个栅电极。 依次形成半导体层和栅极绝缘层,并在其上形成数据线。 数据线包括与栅极线交叉的多条数据线,与数据线连接并靠近栅电极放置的多个源电极,以及与源电极相对于栅电极相对的多个漏电极。 钝化层被沉积并图案化以形成至少暴露漏电极的多个接触孔。 由Ag或Ag合金制成的导电层沉积在钝化层上,并使用含有硝酸铁,硝酸,乙酸,六亚甲基四胺和去离子水的蚀刻剂进行图案化,以形成电连接到漏电极的多个反射膜。