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81. 发明授权

US07227371B2 High performance probe system 有权
标题翻译：高性能探头系统
公开(公告)号：US07227371B2
公开(公告)日：2007-06-05
申请号：US11273889
申请日：2005-11-14
申请人： Charles A. Miller
发明人： Charles A. Miller
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R1/07314 , G01R1/07378 , G01R31/31905 , Y10T29/49117
摘要： A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads.
摘要翻译：用于在集成电路（IC）测试器和要测试的IC的表面上的输入/输出，电源和接地焊盘之间提供信号路径的探针系统包括探针板组件，柔性电缆和一组探针， IC的I / O焊盘。探针板组件包括一个或多个刚性衬底层，其具有形成在衬底层上或衬底层内的迹线和通孔，其提供将测试器连接到访问IC的一些衬垫的探针的相对低带宽的信号路径。柔性电缆提供相对高带宽的信号路径，将测试仪连接到访问IC其他焊盘的探针。

82. 发明授权

US06999987B1 Screening and survey selection system and method of operating the same 有权
标题翻译：筛选和调查选择系统及操作方法
公开(公告)号：US06999987B1
公开(公告)日：2006-02-14
申请号：US09695955
申请日：2000-10-25
申请人： Michael David Billingsley , Gary Crance , Michael J. Cunningham , Anderson Greene , Charles A. Miller , Edwin Franklin Shaw
发明人： Michael David Billingsley , Gary Crance , Michael J. Cunningham , Anderson Greene , Charles A. Miller , Edwin Franklin Shaw
IPC分类号： G06F15/16
CPC分类号： G06Q30/02 , G06Q30/0203
摘要： A screening and survey selection system, method of screening and selecting for a survey and a computer system employing the system and method. In one embodiment, the screening and survey selection system includes a survey queue having a plurality of queue slots, each of the plurality of queue slots including a survey available for a respondent. The screening and survey selection system also includes a random number generator that generates a number pertaining to a selected one of the plurality of queue slots as a function of at least one characteristic associated with the respondent. The screening and survey selection system still further includes a screener block question generator that develops a plurality of screener block questions that determine if the respondent is qualified to participate in a survey corresponding to the selected one of the plurality of queue slots.
摘要翻译：筛选和调查选择系统，筛选选择方法和采用该系统和方法的计算机系统。在一个实施例中，筛选和调查选择系统包括具有多个队列时隙的调查队列，多个队列时隙中的每一个包括可用于被访者的调查。筛选和调查选择系统还包括随机数生成器，其随着与被调查者相关联的至少一个特征的函数产生与所选择的多个队列时隙中的一个相关联的号码。筛选和调查选择系统还包括筛选器块问题生成器，其产生多个筛选器块问题，其确定答复者是否有资格参与对应于多个队列时隙中所选择的一个的调查。

83. 发明授权

US06812691B2 Compensation for test signal degradation due to DUT fault 失效
标题翻译：由于DUT故障引起的测试信号劣化的补偿
公开(公告)号：US06812691B2
公开(公告)日：2004-11-02
申请号：US10193831
申请日：2002-07-12
申请人： Charles A. Miller
发明人： Charles A. Miller
IPC分类号： G01R3126
CPC分类号： G01R31/3191 , G01R31/31723 , G01R31/31908 , G01R31/31924
摘要： An electronic device tester channel transmits a single test signal to multiple terminals of electronic devices under test (DUTs) through a set of isolation resistors. The tester channel employs feedback to automatically adjust the test signal voltage to compensate for affects of faults at any of the DUT terminals to prevent the faults from substantially affecting the test signal voltage.
摘要翻译：电子设备测试仪通道通过一组隔离电阻将单个测试信号发送到被测电子设备（DUT）的多个终端。测试仪通道采用反馈自动调整测试信号电压，以补偿任何DUT端子故障的影响，以防止故障基本上影响测试信号电压。

84. 发明授权

US06680659B2 Integrated circuit interconnect system 失效
公开(公告)号：US06680659B2
公开(公告)日：2004-01-20
申请号：US10133062
申请日：2002-04-26
申请人： Charles A. Miller
发明人： Charles A. Miller
IPC分类号： H03H701
CPC分类号： H01L23/60 , H01L23/5227 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/48091 , H01L2224/4813 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01039 , H01L2924/01074 , H01L2924/01079 , H01L2924/01083 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： In an interconnect system for providing access to a common I/O terminal for multiple circuit devices such as drivers, receivers and electrostatic protection devices implemented on an IC, each such device is provided with a separate contact pad within the IC. The contact pads are linked to one another and to the IC I/O terminal though inductive conductors such as bond wires, metalization layer traces in the IC, or legs of a forked, lithographically-defined spring contact formed on the IC. The conductor inductance isolates the capacitance of the circuit devices from one another, thereby improving characteristics of the frequency response of the interconnect system. The inductances of the conductors and various capacitances of the interconnect system are also appropriately adjusted to optimize desired interconnect system frequency response characteristics.

85. 发明授权

US06622103B1 System for calibrating timing of an integrated circuit wafer tester 失效
标题翻译：用于校准集成电路晶片测试仪的时序的系统
公开(公告)号：US06622103B1
公开(公告)日：2003-09-16
申请号：US09598399
申请日：2000-06-20
申请人： Charles A. Miller
发明人： Charles A. Miller
IPC分类号： G01R3126
CPC分类号： G01R31/318385 , G01R31/31905 , G01R31/3191
摘要： A timing calibration system for a wafer level integrated circuit (IC) tester is disclosed. The tester includes channels linked by paths through an interconnect system to pads of the IC. During a test each channel may send a test signal edge to an IC pad following a clock signal edge with a delay including “programmable drive” delay and “drive calibration” delay components, or may sample an IC output signal following the clock signal edge with a delay including “programmable compare” delay and adjustable “compare calibration” delay components. The interconnect system also links a spare channel to a point on the IC. To adjust the compare calibration delay of each channel, the interconnect system sequentially connects the tester channels to interconnect areas on a “calibration” wafer instead of to the IC on the wafer to be tested. Each interconnect area provides a path linking a channel to be calibrated to the spare channel. With the programmable drive delay of the channel being calibrated and the programmable compare and compare calibration delays of the spare channel set to standard values, the drive calibration delay of the channel being calibrated is adjusted so it sends a test signal edge to the spare channel close to when the spare channel samples it. Pairs of tester channels are then interconnected through another wafer interconnect area. Each channel then sends a test signal edge to the other tester channel with a standard delay following a clock signal edge to provide a reference for calibrating the receiving channel's compare calibration delay.
摘要翻译：公开了一种用于晶片级集成电路（IC）测试仪的定时校准系统。测试仪包括通过互连系统通过IC焊盘连接的通道。在测试期间，每个通道可以在具有包括“可编程驱动器”延迟和“驱动校准”延迟组件的延迟的时钟信号边沿之后向IC垫发送测试信号边沿，或者可以采用时钟信号边沿之后的IC输出信号延迟包括“可编程比较”延迟和可调“比较校准”延迟组件。互连系统还将备用通道连接到IC上的一个点。为了调整每个通道的比较校准延迟，互连系统顺序地将测试仪通道连接到“校准”晶片上的互连区域，而不是连接到要测试的晶片上的IC。每个互连区域提供将要校准的信道链接到备用信道的路径。随着通道的可编程驱动延迟被校准，并且可编程比较和比较备用通道的校准延迟设置为标准值，校准的通道的驱动校准延迟被调整，以便将测试信号边沿发送到备用通道关闭当备用通道采样时。然后，一对测试仪通道通过另一个晶片互连区互连。然后，每个通道在时钟信号边沿之后以标准延迟将测试信号边沿发送到另一个测试仪通道，以提供用于校准接收通道的比较校准延迟的参考。

86. 发明授权

US06606014B2 Filter structures for integrated circuit interfaces 失效
标题翻译：集成电路接口的滤波器结构
公开(公告)号：US06606014B2
公开(公告)日：2003-08-12
申请号：US09816889
申请日：2001-03-23
申请人： Charles A. Miller
发明人： Charles A. Miller
IPC分类号： H01P104
CPC分类号： H05K1/025 , H01L2224/48091 , H01L2924/30107 , H01L2924/3011 , H03H7/0115 , H03H7/38 , H03H2001/0085 , H05K1/0216 , H05K1/0231 , H05K1/0233 , H05K1/113 , H05K1/116 , H05K1/162 , H05K3/3421 , H05K3/429 , H05K2201/09263 , H05K2201/09454 , H05K2201/09672 , H05K2201/09727 , H05K2201/10689 , H01L2924/00014 , H01L2924/00
摘要： An interconnect system for linking integrated circuits (ICs) mounted on a surface of a printed circuit board (PCB) includes a trace positioned below the surface, one or more vias linking the trace to the surface of the PCB, and other conductors linking pads on the ICs to the vias. Impedances of the various components of the interconnect system are sized relative to one another to optimize interconnect system frequency response.
摘要翻译：用于连接安装在印刷电路板（PCB）表面上的集成电路（IC）的互连系统包括位于表面下方的迹线，将迹线连接到PCB的表面的一个或多个通孔以及将PCB上的其它导体 IC到通孔。互连系统的各种组件的阻抗相对于彼此大小，以优化互连系统的频率响应。

87. 发明授权

US06559671B2 Efficient parallel testing of semiconductor devices using a known good device to generate expected responses 失效
公开(公告)号：US06559671B2
公开(公告)日：2003-05-06
申请号：US10208173
申请日：2002-07-29
申请人： Charles A. Miller , Richard S. Roy
发明人： Charles A. Miller , Richard S. Roy
IPC分类号： G01R3126
CPC分类号： G01R31/3193 , G01R31/31905
摘要： A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.

88. 发明授权

US06538538B2 High frequency printed circuit board via 失效
公开(公告)号：US06538538B2
公开(公告)日：2003-03-25
申请号：US09761352
申请日：2001-01-16
申请人： Emad B. Hreish , Charles A. Miller
发明人： Emad B. Hreish , Charles A. Miller
IPC分类号： H01P308
CPC分类号： H03H7/38 , H03H7/0115 , H03H7/075 , H03H7/1758 , H03H2001/0085 , H05K1/0216 , H05K1/0231 , H05K1/0233 , H05K1/0251 , H05K1/113 , H05K1/116 , H05K1/162 , H05K3/3421 , H05K3/429 , H05K2201/09263 , H05K2201/09454 , H05K2201/09672 , H05K2201/09727 , H05K2201/10689
摘要： A printed circuit board (PCB) via, providing a conductor extending vertically between microstrip or stripline conductors formed on separate layers of a PCB, includes a conductive pad surrounding the conductor and embedded within the PCB between those PCB layers. The pad's shunt capacitance and the magnitudes of capacitances of other portions of the via are sized relative to the conductor's inherent inductance to optimize frequency response characteristics of the via.

89. 发明授权

US06501343B2 Integrated circuit tester with high bandwidth probe assembly 失效
标题翻译：具有高带宽探头组合的集成电路测试仪
公开(公告)号：US06501343B2
公开(公告)日：2002-12-31
申请号：US09805668
申请日：2001-03-13
申请人： Charles A. Miller
发明人： Charles A. Miller
IPC分类号： H03H738
CPC分类号： G01R1/073 , G01R1/06766 , G01R1/06772
摘要： Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.
摘要翻译：这里描述的是提供用于在集成电路（IC）和IC测试器的接合焊盘之间传送高频信号的信号路径的探针卡组件。通过沿着信号路径适当地分布，调整和阻抗匹配电阻，电容和电感阻抗值来优化探针卡组件的频率响应，使得互连系统作为适当调节的巴特沃斯或切比雪夫滤波器。

90. 发明授权

US06452411B1 Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses 失效
标题翻译：使用已知的良好设备对集成电路设备进行有效的并行测试以产生预期响应
公开(公告)号：US06452411B1
公开(公告)日：2002-09-17
申请号：US09260460
申请日：1999-03-01
申请人： Charles A. Miller , Richard S. Roy
发明人： Charles A. Miller , Richard S. Roy
IPC分类号： G01R3126
CPC分类号： G01R31/3193 , G01R31/31905
摘要： A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.
摘要翻译：公开了一种用于测试集成电路器件的系统，其中测试器通过通道与已知的良好器件进行通信。测试仪 - DUT接口电路用于监视通道，同时测试人员将数据作为测试序列的一部分写入已知的良好设备中的位置。作为响应，接口电路将数据写入被测设备（DUT）中的每一个中的相应位置。当测试仪从已知的良好设备（KGD）中的位置读取时，接口电路监视通道，并且响应于从被测设备中的相应位置读取的DUT数据和从KGD获得的预期响应之间的比较。

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