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81. 发明授权

US08442230B1 Enhanced high availability for group VPN in broadcast environment 有权
标题翻译：在广播环境中增强组VPN的高可用性
公开(公告)号：US08442230B1
公开(公告)日：2013-05-14
申请号：US12952623
申请日：2010-11-23
申请人： Anthony Ng , Chih-Wei Chao , Nagavenkata Suresh Melam , Nilesh Kumar Maheshwari
发明人： Anthony Ng , Chih-Wei Chao , Nagavenkata Suresh Melam , Nilesh Kumar Maheshwari
IPC分类号： H04L9/00
CPC分类号： H04L43/10 , H04L9/0822 , H04L63/0272 , H04L63/065 , H04L63/164
摘要： A light-weight resilient mechanism is used to synchronize server secure keying data with member devices in a highly-scalable distributed group virtual private network (VPN). A server device generates an initial secure keying data set, for the VPN, that includes a first version identifier, and sends, to member devices and via point-to-point messages, the secure keying data set. The server device sends, to the member devices, heartbeat push messages including the first version identifier. The server device generates an updated secure keying data set with a second version identifier and sends, to the member devices, a key push message that includes the updated data set. The server device sends, to the member devices, heartbeat push messages including the second version identifier. Member devices may use the first and second version identifiers to confirm that secure keying data sets are current and quickly identify if updates are missed.
摘要翻译：轻量级的弹性机制用于将服务器安全密钥数据与高度可扩展的分布式组虚拟专用网（VPN）中的成员设备同步。服务器设备为VPN生成包括第一版本标识符的初始安全密钥数据集，并向成员设备发送安全密钥数据集，并通过点对点消息发送安全密钥数据集。服务器设备向成员设备发送包括第一版本标识符的心跳推送消息。服务器设备生成具有第二版本标识符的更新的安全密钥数据集，并向成员设备发送包括更新的数据集的密钥推送消息。服务器设备向成员设备发送包括第二版本标识符的心跳推送消息。成员设备可以使用第一和第二版本标识符来确认安全密钥数据集是当前的，并且快速识别是否错过更新。

82. 发明申请

US20110318858A1 METHOD FOR FABRICATING LIGHT EMITTING DIODE CHIP 有权
公开(公告)号：US20110318858A1
公开(公告)日：2011-12-29
申请号：US13220694
申请日：2011-08-30
申请人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
发明人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
IPC分类号： H01L33/44
CPC分类号： H01L33/387 , H01L33/382 , H01L33/44
摘要： A method for fabricating a light emitting diode chip is provided. Firstly, a semiconductor device layer is formed on a substrate. Afterwards, a current spreading layer is formed on a portion of the semiconductor device layer. Then, a current blocking layer and a passivation layer are formed on a portion of the semiconductor device layer not covered by the current spreading layer. Finally, a first electrode is formed on the current blocking layer and the current spreading layer. Moreover, a second electrode is formed on the semiconductor device layer.

83. 发明申请

US20110159613A1 Method for Fabricating LED Chip Comprising Reduced Mask Count and Lift-Off Processing 有权
公开(公告)号：US20110159613A1
公开(公告)日：2011-06-30
申请号：US13046619
申请日：2011-03-11
申请人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
发明人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
IPC分类号： H01L33/48
CPC分类号： H01L33/44 , H01L33/387 , Y10S438/951
摘要： A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

84. 发明申请

US20110159612A1 Method for Fabricating LED Chip Comprising Reduced Mask Count and Lift-Off Processing 有权
公开(公告)号：US20110159612A1
公开(公告)日：2011-06-30
申请号：US13046576
申请日：2011-03-11
申请人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
发明人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
IPC分类号： H01L33/52
CPC分类号： H01L33/44 , H01L33/387 , Y10S438/951
摘要： A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

85. 发明申请

US20100303056A1 PROBABILITY TIME DIVISION MULTIPLEXING POLLING METHOD AND WIRELESS IDENTIFIER READER CONTROLLER THEREOF 有权
标题翻译：可行性时间段多重检测方法及其无线标识符读取器控制器
公开(公告)号：US20100303056A1
公开(公告)日：2010-12-02
申请号：US12491256
申请日：2009-06-25
申请人： Tsu-Kuang Yang , Jen-Yau Kuo , Tung-Hung Lu , Kuo-Shu Luo , Li-Dien Fu , Min-Hsien Weng , Chih-Wei Chao
发明人： Tsu-Kuang Yang , Jen-Yau Kuo , Tung-Hung Lu , Kuo-Shu Luo , Li-Dien Fu , Min-Hsien Weng , Chih-Wei Chao
IPC分类号： H04J3/16 , H04Q5/22
CPC分类号： G08C15/06
摘要： Exemplary embodiments of the present invention illustrate a probability time division multiplexing polling method and a wireless identifier reader controller thereof. The probability time division multiplexing polling method is used to control a plurality of wireless identifier readers to be turned on or off. First, one of the wireless identifier readers is randomly selected according to a probability model, wherein the probability model presents the probabilities for detecting an identifier tag of the wireless identifier readers. Then, the selected wireless identifier reader is turned on for a predetermined time period.
摘要翻译：本发明的示例性实施例示出了概率时分复用轮询方法及其无线标识符读取器控制器。概率时分复用轮询方法用于控制多个无线标识符读取器被打开或关闭。首先，根据概率模型随机选择无线标识符读取器之一，其中概率模型呈现用于检测无线标识符读取器的标识符标签的概率。然后，所选择的无线标识符读取器在预定时间段内被接通。

86. 发明申请

US20100221494A1 METHOD FOR FORMING SEMICONDUCTOR LAYER 审中-公开
标题翻译：形成半导体层的方法
公开(公告)号：US20100221494A1
公开(公告)日：2010-09-02
申请号：US12465655
申请日：2009-05-14
申请人： Chang-Ming Lu , Chih-Wei Chao , Te-Chung Wang , Kuo-Lung Fang , Chun-Jong Chang
发明人： Chang-Ming Lu , Chih-Wei Chao , Te-Chung Wang , Kuo-Lung Fang , Chun-Jong Chang
IPC分类号： B32B3/00 , H01L21/20
CPC分类号： H01L21/02647 , C30B25/02 , C30B29/406 , H01L21/0237 , H01L21/02433 , H01L21/02639 , Y10T428/24479
摘要： A method for forming a semiconductor layer includes following steps. First, an epitaxial substrate having at least a first growth region and at least a second growth region is provided. An area ratio of C plane to R plane in the first growth region is greater than 52/48. An epitaxial process is then performed on the epitaxial substrate to form a semiconductor layer. During the epitaxial process, a semiconductor material is selectively grown on the first growth region, and then the semiconductor material is laterally overgrown on the second growth region and covers the same.
摘要翻译：形成半导体层的方法包括以下步骤。首先，提供具有至少第一生长区和至少第二生长区的外延衬底。第一生长区域中C面与R面的面积比大于52/48。然后在外延衬底上进行外延工艺以形成半导体层。在外延工艺期间，半导体材料选择性地生长在第一生长区域上，然后半导体材料在第二生长区域上横向长满而覆盖。

87. 发明授权

US07745826B2 Thin film transistor substrate, electronic apparatus, and methods for fabricating the same 有权
标题翻译：薄膜晶体管基板，电子设备及其制造方法
公开(公告)号：US07745826B2
公开(公告)日：2010-06-29
申请号：US12249968
申请日：2008-10-13
申请人： Ming-Wei Sun , Chih-Wei Chao
发明人： Ming-Wei Sun , Chih-Wei Chao
IPC分类号： H01L29/04
CPC分类号： H01L27/1296 , H01L29/66757
摘要： A TFT substrate includes a substrate and at least a TFT disposed thereon. The TFT includes a semiconductor island and at least a gate. The semiconductor island has a source region, a drain region, and a channel region interposed therebetween. The semiconductor island has sub-grain boundaries. The gate corresponds to the channel region. A first included angle between an extending direction of the gate and a line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 90 degrees. A second included angle between the sub-grain boundaries in the channel region and the line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 0 degree or 90 degrees. Additionally, a method of fabricating a TFT substrate, an electronic apparatus, and a method of fabricating the electronic apparatus are also provided.
摘要翻译： TFT基板包括基板和至少设置在其上的TFT。 TFT包括半导体岛和至少一个栅极。半导体岛具有源极区，漏极区和插入其间的沟道区。半导体岛具有亚晶界。门对应于通道区域。栅极的延伸方向与连接源极区域的质心与漏极区域的质心之间的第一夹角基本上不等于90度。沟道区域中的子晶界之间的第二夹角与将源极区域的质心与漏极区域的质心连接的线基本上不等于0度或90度。此外，还提供了制造TFT基板的方法，电子设备和制造该电子设备的方法。

88. 发明申请

US20100051950A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THEREOF 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US20100051950A1
公开(公告)日：2010-03-04
申请号：US12337583
申请日：2008-12-17
申请人： Ming-Wei Sun , Chih-Wei Chao
发明人： Ming-Wei Sun , Chih-Wei Chao
IPC分类号： H01L29/04 , H01L21/84 , H01L21/36
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/02595 , H01L21/268 , H01L27/12 , H01L27/1214 , H01L27/1274 , H01L27/1285 , H01L29/04 , H01L29/66757
摘要： A thin film transistor array substrate includes a substrate, a plurality of poly-silicon islands and a plurality of gates. The substrate has a display region, a gate driver region and a source driver region. Each poly-silicon island disposed on the substrate has a source region, a drain region and a channel region disposed therebetween. The poly-silicon islands include several first poly-silicon islands and several second poly-silicon islands. The first poly-silicon islands having main grain boundaries and sub grain boundaries are only disposed within the display region and the gate driver region. The main grain boundaries of the first poly-silicon islands are only disposed within the source regions and/or the drain regions. The second poly-silicon islands are disposed in the source driver region. Grain sizes of the first poly-silicon islands are substantially different from those of the second poly-silicon islands. Gates corresponding to the channel regions are disposed on the substrate.
摘要翻译：薄膜晶体管阵列基板包括基板，多个多晶硅岛和多个栅极。衬底具有显示区域，栅极驱动器区域和源极驱动器区域。设置在基板上的每个多硅岛具有源极区域，漏极区域和设置在其间的沟道区域。多晶硅岛包括几个第一多晶硅岛和几个第二多晶硅岛。具有主晶粒边界和子晶界的第一多晶硅岛仅设置在显示区域和栅极驱动器区域内。第一多晶硅岛的主晶粒边界仅设置在源区和/或漏区内。第二多晶硅岛设置在源极驱动器区域中。第一多晶硅岛的晶粒尺寸与第二多晶硅岛的晶粒尺寸基本不同。对应于沟道区的栅极设置在衬底上。

89. 发明申请

US20100015742A1 METHOD FOR FABRICATING LIGHT EMITTING DIODE CHIP 有权
标题翻译：用于制造发光二极管芯片的方法
公开(公告)号：US20100015742A1
公开(公告)日：2010-01-21
申请号：US12252370
申请日：2008-10-16
申请人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
发明人： Kuo-Lung Fang , Chien-Sen Weng , Chih-Wei Chao
IPC分类号： H01L21/00
CPC分类号： H01L33/44 , H01L33/387 , Y10S438/951
摘要： A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.
摘要翻译：提供一种制造发光二极管芯片的方法。在该方法中，应用半色调掩模处理，灰度色调处理或多色调掩模处理，并与剥离处理相结合，以进一步减少发光二极管芯片的处理步骤。在本发明中，一些部件也可以通过相同的工艺同时形成，以减少发光二极管芯片的工艺步骤。因此，本发明中提供的发光二极管的制造方法降低了用于制造发光二极管的成本和时间。

90. 发明授权

US07572700B2 EEPROM and method of manufacturing the same 有权
标题翻译： EEPROM及其制造方法
公开(公告)号：US07572700B2
公开(公告)日：2009-08-11
申请号：US12180521
申请日：2008-07-26
申请人： Chih-Wei Chao , Chin-Wei Hu , Chi-Wen Chen
发明人： Chih-Wei Chao , Chin-Wei Hu , Chi-Wen Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/115 , H01L27/11558 , H01L27/1203
摘要： An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer. A first dielectric layer is formed on the first semiconductor layer, and a first floating gate is formed on the first dielectric layer. A second source and a second drain are located at two opposing sides of the second semiconductor layer. A second dielectric layer is formed on the second semiconductor layer, and a second floating gate is formed on the second dielectric layer. The first floating gate and the second floating gate are electrically connected.
摘要翻译： EEPROM包括基板，形成在基板上的第一半导体层和第二半导体层。第一半导体层通过沟槽与第二半导体层隔离。第一源极和第一漏极位于第一半导体层的相对两侧。在第一半导体层上形成第一电介质层，在第一电介质层上形成第一浮栅。第二源极和第二漏极位于第二半导体层的两个相对侧。在第二半导体层上形成第二电介质层，在第二电介质层上形成第二浮栅。第一浮栅和第二浮栅电连接。

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