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81. 发明申请

US20120168955A1 Integrated Circuit Pattern and Method 有权
标题翻译：集成电路图案及方法
公开(公告)号：US20120168955A1
公开(公告)日：2012-07-05
申请号：US12983832
申请日：2011-01-03
申请人： Shih-Hung Chen , Hang-Ting Lue
发明人： Shih-Hung Chen , Hang-Ting Lue
IPC分类号： H01L23/538 , H01L21/3205
CPC分类号： H01L27/11573 , H01L21/0337 , H01L21/0338 , H01L23/528 , H01L27/11565 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.
摘要翻译：集成电路图案包括具有X和Y方向部分的一组材料线。 X和Y方向部分具有第一和第二间距，第二间距比第一间距大至少3倍。 X方向部分是平行的，并且Y方向部分是平行的。 Y方向部分的端部区域包括主线部分和偏移部分。偏移部分包括与主线部分间隔开并电连接到主线部分的偏移元件。偏移部分限定用于后续图案转印过程的接触区域。为了在集成电路处理过程中使用的多重图形化方法提供用于随后的图案转印过程的接触区域。

82. 发明授权

US08169761B2 ESD clamp circuit applied to power amplifier 有权
标题翻译： ESD钳位电路应用于功率放大器
公开(公告)号：US08169761B2
公开(公告)日：2012-05-01
申请号：US12400799
申请日：2009-03-10
申请人： Chih-Ting Yeh , Yung-Chih Liang , Shih-Hung Chen
发明人： Chih-Ting Yeh , Yung-Chih Liang , Shih-Hung Chen
IPC分类号： H02H9/00
CPC分类号： H03F1/523 , H01L27/0266 , H03F2200/441
摘要： An ESD clamp circuit applied to a power amplifier is provided. The ESD clamp circuit includes a first line, a second line, a first circuit, a second circuit, an ESD detecting unit, a buffer unit, and an ESD clamp unit. The first line is coupled to the output terminal of the power amplifier. The first circuit is coupled to the first line. The second circuit is coupled to the first circuit. The ESD detecting unit is coupled to the first circuit and the second line. The buffer unit is coupled to the second circuit, the second line and the ESD detecting unit. The ESD clamp unit is coupled to the buffer unit, the first line and the second line. Therefore, at normal operation mode, the problem of signal loss caused by the leakage current of ESD clamp circuit can be avoided.
摘要翻译：提供了应用于功率放大器的ESD钳位电路。 ESD钳位电路包括第一线，第二线，第一电路，第二电路，ESD检测单元，缓冲单元和ESD钳位单元。第一行耦合到功率放大器的输出端。第一电路耦合到第一线。第二电路耦合到第一电路。 ESD检测单元耦合到第一电路和第二线。缓冲单元耦合到第二电路，第二线路和ESD检测单元。 ESD钳位单元耦合到缓冲单元，第一线和第二线。因此，在正常工作模式下，可以避免由ESD钳位电路的漏电流引起的信号损失问题。

83. 发明授权

US08102702B2 Phase change memory and operation method of the same 有权
标题翻译：相变存储器和操作方法相同
公开(公告)号：US08102702B2
公开(公告)日：2012-01-24
申请号：US12545294
申请日：2009-08-21
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2013/0092
摘要： An operation method of phase change memory (PCM) is provided. The operation method includes applying a RESET pulse to a phase change material of the PCM, wherein the RESET pulse has a profile with a first tail such that a plurality of seeds are formed in the phase change material. Due to the design of the RESET pulse in the operation method, it can speed up the crystal process.
摘要翻译：提供了相变存储器（PCM）的操作方法。该操作方法包括将RESET脉冲施加到PCM的相变材料，其中RESET脉冲具有带有第一尾部的轮廓，使得在相变材料中形成多个种子。由于操作方法中RESET脉冲的设计，可以加快晶体过程。

84. 发明授权

US08102001B2 Initial-on SCR device for on-chip ESD protection 有权
标题翻译：初始化SCR器件，用于片上ESD保护
公开(公告)号：US08102001B2
公开(公告)日：2012-01-24
申请号：US12891474
申请日：2010-09-27
申请人： Ming-Dou Ker , Shih-Hung Chen , Kun-Hsien Lin
发明人： Ming-Dou Ker , Shih-Hung Chen , Kun-Hsien Lin
IPC分类号： H01L23/62
CPC分类号： H01L23/62 , H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.
摘要翻译：一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，形成在衬底中的第二阱，形成在第一阱中的第一p型区用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接到PMOS晶体管的第二扩散区域。

85. 发明授权

US07993962B2 I-shaped phase change memory cell 有权
标题翻译： I形相变存储单元
公开(公告)号：US07993962B2
公开(公告)日：2011-08-09
申请号：US12614902
申请日：2009-11-09
申请人： Shih-Hung Chen , Hsiang-Lan Lung
发明人： Shih-Hung Chen , Hsiang-Lan Lung
IPC分类号： H01L21/06
CPC分类号： H01L27/2436 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact surface in electrical contact with the second electrode; and a kernel member disposed between and in electrical contact with the upper and lower phase change members. The phase change cell is formed of material having at least two solid phases, and the lateral extent of the upper and lower phase change members is substantially greater than that of the kernel member. An intermediate insulating layer is disposed between the upper and lower phase change members adjacent to the kernel member.
摘要翻译：存储器件包括垂直分离并具有相互相对的接触表面的两个电极，它们位于相变单元之间。相变单元包括上相变构件，具有与第一电极电接触的接触表面; 下部相变构件，具有与第二电极电接触的接触表面; 以及设置在上部和下部相变构件之间并与之电连接的内部构件。相变单元由具有至少两个固相的材料形成，并且上下相变构件的横向范围基本上大于内核构件的横向范围。中间绝缘层设置在与内核构件相邻的上下相变构件之间。

86. 发明授权

US07956358B2 I-shaped phase change memory cell with thermal isolation 有权
标题翻译：具有热隔离的I形相变存储单元
公开(公告)号：US07956358B2
公开(公告)日：2011-06-07
申请号：US11348846
申请日：2006-02-07
申请人： Shih Hung Chen
发明人： Shih Hung Chen
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1246 , H01L45/144 , H01L45/1666
摘要： A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact surface in electrical contact with the second electrode; and a kernel member disposed between and in electrical contact with the upper and lower phase change members. The phase change cell is formed of material having at least two solid phases, and the lateral extent of the upper and lower phase change members is substantially greater than that of the kernel member. An intermediate insulating layer is disposed between the upper and lower phase change members adjacent to the kernel member.
摘要翻译：存储器件包括垂直分离并具有相互相对的接触表面的两个电极，它们位于相变单元之间。相变单元包括上相变构件，具有与第一电极电接触的接触表面; 下部相变构件，具有与第二电极电接触的接触表面; 以及设置在上部和下部相变构件之间并与之电连接的内部构件。相变单元由具有至少两个固相的材料形成，并且上下相变构件的横向范围基本上大于内核构件的横向范围。中间绝缘层设置在与内核构件相邻的上下相变构件之间。

87. 发明申请

US20100276654A1 Low Operational Current Phase Change Memory Structures 有权
标题翻译：低运行电流相变存储器结构
公开(公告)号：US20100276654A1
公开(公告)日：2010-11-04
申请号：US12433573
申请日：2009-04-30
申请人： Shih-Hung Chen , Yi-Chou Chen
发明人： Shih-Hung Chen , Yi-Chou Chen
IPC分类号： H01L47/00
CPC分类号： H01L45/122 , H01L27/2436 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1616 , H01L45/1641 , H01L45/1675 , Y10S977/943
摘要： Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency.
摘要翻译：与传统的蘑菇型存储器单元相比，本文所述的存储单元在有源区域的横向边缘处具有增加的电流密度，从而提高了操作电流效率。

88. 发明申请

US20100149703A1 ESD CLAMP CIRCUIT APPLIED TO POWER AMPLIFIER 有权
标题翻译： ESD钳位电路适用于功率放大器
公开(公告)号：US20100149703A1
公开(公告)日：2010-06-17
申请号：US12400799
申请日：2009-03-10
申请人： Chih-Ting Yeh , Yung-Chih Liang , Shih-Hung Chen
发明人： Chih-Ting Yeh , Yung-Chih Liang , Shih-Hung Chen
IPC分类号： H02H9/04
CPC分类号： H03F1/523 , H01L27/0266 , H03F2200/441
摘要： An ESD clamp circuit applied to a power amplifier is provided. The ESD clamp circuit includes a first line, a second line, a first circuit, a second circuit, an ESD detecting unit, a buffer unit, and an ESD clamp unit. The first line is coupled to the output terminal of the power amplifier. The first circuit is coupled to the first line. The second circuit is coupled to the first circuit. The ESD detecting unit is coupled to the first circuit and the second line. The buffer unit is coupled to the second circuit, the second line and the ESD detecting unit. The ESD clamp unit is coupled to the buffer unit, the first line and the second line. Therefore, at normal operation mode, the problem of signal loss caused by the leakage current of ESD clamp circuit can be avoided.
摘要翻译：提供了应用于功率放大器的ESD钳位电路。 ESD钳位电路包括第一线，第二线，第一电路，第二电路，ESD检测单元，缓冲单元和ESD钳位单元。第一行耦合到功率放大器的输出端。第一电路耦合到第一线。第二电路耦合到第一电路。 ESD检测单元耦合到第一电路和第二线。缓冲单元耦合到第二电路，第二线路和ESD检测单元。 ESD钳位单元耦合到缓冲单元，第一线和第二线。因此，在正常工作模式下，可以避免由ESD钳位电路的漏电流引起的信号损失问题。

89. 发明授权

US07635855B2 I-shaped phase change memory cell 有权
标题翻译： I形相变存储单元
公开(公告)号：US07635855B2
公开(公告)日：2009-12-22
申请号：US11348848
申请日：2006-02-07
申请人： Shih Hung Chen , Hsiang Lan Lung
发明人： Shih Hung Chen , Hsiang Lan Lung
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact surface in electrical contact with the second electrode; and a kernel member disposed between and in electrical contact with the upper and lower phase change members. The phase change cell is formed of material having at least two solid phases, and the lateral extent of the upper and lower phase change members is substantially greater than that of the kernel member. An intermediate insulating layer is disposed between the upper and lower phase change members adjacent to the kernel member.
摘要翻译：存储器件包括垂直分离并具有相互相对的接触表面的两个电极，它们位于相变单元之间。相变单元包括上相变构件，具有与第一电极电接触的接触表面; 下部相变构件，具有与第二电极电接触的接触表面; 以及设置在上部和下部相变构件之间并与之电连接的内部构件。相变单元由具有至少两个固相的材料形成，并且上下相变构件的横向范围基本上大于内核构件的横向范围。中间绝缘层设置在与内核构件相邻的上下相变构件之间。

90. 发明授权

US07598512B2 Thin film fuse phase change cell with thermal isolation layer and manufacturing method 有权
标题翻译：薄膜保险丝相变电池与隔热层及制造方法
公开(公告)号：US07598512B2
公开(公告)日：2009-10-06
申请号：US11466421
申请日：2006-08-22
申请人： Shih Hung Chen
发明人： Shih Hung Chen
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/1293 , H01L45/148 , H01L45/1675
摘要： A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. The bridge comprises an active layer of memory material on the first side having at least two solid phases and a blanket of thermal insulating material overlying the memory material having thermal conductivity less than that of an overlying electrically insulating layer.
摘要翻译：一种存储器件，包括具有顶侧的第一电极，具有顶侧的第二电极和位于第一电极和第二电极之间的绝缘构件。绝缘构件在第一电极的顶侧附近和第二电极的顶侧之间具有在第一和第二电极之间的厚度。记忆材料桥跨越绝缘构件，并且在绝缘构件之间限定了第一和第二电极之间的电极间路径。提供这样的存储单元阵列。该桥包括在第一侧上具有至少两个固相的存储材料的有源层和覆盖存储材料的热绝缘材料的毯子，其热导率小于上覆电绝缘层的热导率。

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