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    • 86. 发明申请
    • DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
    • 显示装置及其制造方法
    • US20100006832A1
    • 2010-01-14
    • US12561218
    • 2009-09-16
    • Joon-hak OhMun-pyo HongBo-sung kimYong-uk Lee
    • Joon-hak OhMun-pyo HongBo-sung kimYong-uk Lee
    • H01L51/10H01L51/40
    • H01L51/0545B82Y30/00H01L27/3244H01L51/0005H01L51/0016H01L51/0558
    • According to an embodiment of the present invention, a manufacturing method of a display device includes forming a plurality of gate wires comprising a gate electrode on an insulating substrate, forming an electrode layer comprising a source electrode and a drain electrode spaced apart from each other to define a channel region on the gate electrode interposed therebetween, forming a first barrier wall having a first opening for exposing the channel region, a portion of the source electrode, and a portion of the drain electrode on the electrode layer where the first barrier wall has a surface, forming a shielding film to cover the channel region inside the first opening, treating the surface of the first barrier wall, removing the shielding film, and forming an organic semiconductor layer inside the first opening.
    • 根据本发明的实施例,显示装置的制造方法包括在绝缘基板上形成包括栅电极的多条栅极线,形成包括彼此间隔开的源电极和漏极的电极层, 在所述栅极电极之间限定沟道区,形成第一阻挡壁,所述第一阻挡壁具有用于暴露所述沟道区的第一开口,所述源极的一部分以及所述第一阻挡壁具有的所述电极层上的所述漏电极的一部分 形成屏蔽膜以覆盖第一开口内的沟道区域,处理第一阻挡壁的表面,去除屏蔽膜,以及在第一开口内部形成有机半导体层。
    • 88. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL FOR A LIQUID CRYSTAL DISPLAY AND A METHOD FOR MANUFACTURING THE SAME
    • 用于液晶显示器的薄膜晶体管阵列板及其制造方法
    • US20090179202A1
    • 2009-07-16
    • US12364736
    • 2009-02-03
    • Mun-Pyo HONGWoon-Yong PARKJong-Soo YOON
    • Mun-Pyo HONGWoon-Yong PARKJong-Soo YOON
    • H01L33/00
    • G02F1/13458G02F1/1362G02F1/136227G02F2001/136236H01L27/12H01L27/124H01L27/1288H01L29/41733H01L29/458Y10S438/942Y10S438/947Y10S438/949
    • Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.
    • 制造液晶显示器的简化方法。 通过使用第一掩模在基板上形成包括栅极线,栅极焊盘和栅电极的栅极线。 依次沉积栅极绝缘层,半导体层,欧姆接触层和金属层以制成四层,并通过使用第二掩模的干蚀刻图案化。 此时,四层被图案化以具有网状布局的矩阵并覆盖栅极线。 在显示区域形成露出基板的开口,在周边区域形成露出栅极焊盘的接触孔。 接下来,沉积ITO并且涂覆在ITO上的光致抗蚀剂层。 然后,通过使用第三掩模和干蚀刻对ITO层进行图案化,并且数据导体层和未被ITO层覆盖的欧姆接触层被干蚀刻。 在沉积钝化层之后,通过使用第四掩模形成开口,并蚀刻通过开口的暴露的半导体层以将相邻数据线下的半导体层分离。
    • 89. 发明申请
    • CONTACT STRUCTURES OF WIRINGS AND METHODS FOR MANUFACTURING THE SAME, AND THIN FILM TRANSISTOR ARRAY PANELS INCLUDING THE SAME AND METHODS FOR MANUFACTURING THE SAME
    • 接线端子结构及其制造方法,以及包括其的薄膜晶体管阵列及其制造方法
    • US20080293241A1
    • 2008-11-27
    • US12188272
    • 2008-08-08
    • Mun Pyo HongSang-Gab Kim
    • Mun Pyo HongSang-Gab Kim
    • H01L21/44
    • G02F1/1362G02F1/136286H01L27/124H01L27/1288H01L29/458
    • First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pa and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed. Next, IZO is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively and electrically connected to the drain electrode, the gate pad and the data pad via the inter-layer reaction layers.
    • 首先,将由铝基材料制成的导电材料沉积并图案化以形成包括栅极线,栅极焊盘和栅电极的栅极线。 形成栅绝缘层,依次形成半导体层和欧姆接触层。 接下来,沉积包括下层Cr的导体层和铝基材料的上层,并构图以形成包括与栅极线相交的数据线,源电极,漏电极和数据焊盘的数据线。 然后,沉积并图案化钝化层以形成分别暴露漏电极,栅极焊盘和数据焊盘的接触孔。 接下来,沉积非晶硅层,执行退火处理,以在漏电极,栅极pa和数据焊盘上形成通过接触孔露出的层间反应层。 然后,去除非晶硅层。 接下来,IZO被沉积和图案化以分别形成像素电极,冗余栅极焊盘和冗余数据焊盘,并经由层间反应层电连接到漏电极,栅极焊盘和数据焊盘。