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81. 发明授权

US06468877B1 Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner 有权
标题翻译：通过使用一次性间隔件/衬垫在栅电极的边缘下形成气隙的方法
公开(公告)号：US06468877B1
公开(公告)日：2002-10-22
申请号：US09907651
申请日：2001-07-19
申请人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
发明人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
IPC分类号： H01L2176
CPC分类号： H01L21/7682 , H01L21/764 , H01L21/823468 , H01L29/4983
摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.
摘要翻译：一种制造半导体器件的气隙间隔物的方法，包括以下步骤。提供具有至少一对限定有源区域的STI的半导体衬底。在有源区内的基板上形成栅电极。栅电极具有底层栅介电层。在该结构上形成衬里氧化物层，覆盖栅极电介质层的侧壁，栅电极以及栅电极的顶表面。在衬垫氧化物层上形成衬里氮化物层。在结构上形成厚的氧化物层。厚氧化物，衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化，并且在栅电极的任一侧暴露衬里氧化物层。用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层，以在栅电极的任一侧上形成横截面倒置的T形开口。在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层，其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口，并且其中气隙间隔物邻近倒置的底部形成 T形开口。蚀刻栅间隔氧化物，衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。

82. 发明授权

US06455377B1 Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) 失效
标题翻译：通过SiGe或多量子阱（MQW）的选择性沉积形成非常高迁移率的垂直沟道晶体管的方法
公开(公告)号：US06455377B1
公开(公告)日：2002-09-24
申请号：US09765040
申请日：2001-01-19
申请人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
发明人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/1054 , H01L29/66916 , H01L29/7827 , H01L29/802
摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.
摘要翻译：一种制造垂直沟道晶体管的方法，包括以下步骤。提供具有上表面的半导体衬底。在半导体衬底上形成高掺杂N型下部外延硅层。在下部外延硅层上形成低掺杂P型中间外延硅层。在中间外延硅层上形成高掺杂N型上部外延硅层。蚀刻下部，中间和上部外延硅层以形成由隔离沟槽限定的外延层堆叠。在隔离槽内形成氧化物。氧化物被蚀刻以在一个隔离沟槽内形成栅极沟槽，暴露外延层堆叠面向栅极沟槽的侧壁。在暴露的外延层堆叠侧壁上形成多量子阱或染色层超晶格。在多量子阱或染色层超晶格上并在栅极沟槽内形成栅介质层。栅极导体层形成在栅极电介质层上，填充栅极沟槽。

83. 发明授权

US06440800B1 Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers 失效
公开(公告)号：US06440800B1
公开(公告)日：2002-08-27
申请号：US09769814
申请日：2001-01-26
申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/365 , H01L29/7827
摘要： A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

84. 发明授权

US06380610B1 Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect 失效
标题翻译：无位错局部氧化硅，抑制窄空间场氧化物稀化效应
公开(公告)号：US06380610B1
公开(公告)日：2002-04-30
申请号：US09257838
申请日：1999-02-25
申请人： Igor V. Peidous , Elgin Quek , Konstantin V. Loiko , David Yeo Yong Hock
发明人： Igor V. Peidous , Elgin Quek , Konstantin V. Loiko , David Yeo Yong Hock
IPC分类号： H01L2358
CPC分类号： H01L21/32 , H01L21/0332 , H01L21/76202 , Y10S438/95
摘要： A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.
摘要翻译：一种用于改善鸟喙控制的氧化面罩的新颖设计，更具体地用于在鸟喙附近调整和平滑场氧化物隔离轮廓。掩模设计对于半微米集成电路技术中的窄场隔离间隔特别有利。掩模在其下边缘处使用薄的氮化硅脚，以允许在氧化的早期阶段氧化物的标称膨胀，从而允许原位应力消除以及氧化物轮廓的平滑化。第二较厚的氮化硅层的悬臂部分在生长速度减慢时在氧化的后期阶段抑制柔性脚的向上移动，由此抑制鸟喙的生长。负责位错生成的剪切应力减少了五十倍。这种应力降低伴随着表面形貌的改善以及窄的氧化物稀化效应的抑制。

85. 发明授权

US09034711B2 LDMOS with two gate stacks having different work functions for improved breakdown voltage 有权
标题翻译： LDMOS具有两个栅极叠层，具有不同的功能，可提高击穿电压
公开(公告)号：US09034711B2
公开(公告)日：2015-05-19
申请号：US13046332
申请日：2011-03-11
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L21/336 , H01L29/78 , H01L29/423 , H01L29/51 , H01L29/49 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/42364 , H01L29/42368 , H01L29/42372 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a second gate stack over the n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, the first and second gate stacks sharing a common gate electrode, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack with a first high-k dielectric and the second gate stack with a second high-k dielectric, and forming the first and second gate stacks with asymmetric dielectrics.
摘要翻译： LDMOS在n漂移区上形成有第二栅极堆叠，其具有与栅极堆叠相同的公共栅电极，并且具有比栅极堆叠更高的功函数。实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二栅极叠层，第二阱，第一和第二栅极堆叠共享公共栅极电极，并且调谐第一和第二栅极堆叠的功函数以获得用于第二栅极堆叠的较高功函数。其他实施例包括用第一高k电介质形成第一栅极堆叠，以及用第二高k电介质形成第二栅极堆叠，以及用不对称电介质形成第一和第二栅极堆叠。

86. 发明授权

US08993407B2 Compact localized RRAM cell structure realized by spacer technology 有权
标题翻译：通过间隔技术实现紧凑的局部RRAM单元结构
公开(公告)号：US08993407B2
公开(公告)日：2015-03-31
申请号：US13683779
申请日：2012-11-21
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2445 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1675 , H01L45/1691
摘要： An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode.
摘要翻译：公开了一种具有垂直BJT选择器的RRAM。实施例包括在衬底中限定STI区域，在衬底中注入掺杂剂以在STI区域的底部周围和下方形成第一极性，在STI区域的相对侧上的阱上的第二极性沟道，以及第一在衬底的表面上的每个通道上的极性有源区域，在有源区域和STI区域上形成RRAM衬垫，在RRAM衬垫上形成牺牲顶部电极，在牺牲顶部电极的相对侧上形成间隔物，注入第二极性在牺牲顶部电极的相对侧上的有源区域中形成掺杂剂，在间隔物附近形成氧化硅，去除形成空腔的牺牲顶部电极的至少一部分，在空腔中形成邻近间隔物的内部间隔物和顶部电极。

87. 发明授权

US08889494B2 Finfet 有权
公开(公告)号：US08889494B2
公开(公告)日：2014-11-18
申请号：US12980371
申请日：2010-12-29
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L21/84 , H01L21/00 , H01L29/78 , H01L29/66
CPC分类号： H01L29/785 , H01L29/0847 , H01L29/66795 , H01L29/78603
摘要： A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.
摘要翻译：翅片型晶体管包括在衬底表面上的用于将晶体管的栅极与衬底隔离的介质层。电介质层包括非选择性蚀刻的表面，以产生翅片结构的顶部，其具有减小横跨晶片的高度变化。翅片型晶体管还可以包括至少低于S / D区的反掺杂区域，以减小寄生电容以改善其性能。

88. 发明申请

US20140167161A1 FLOATING BODY CELL 有权
标题翻译：浮动体细胞
公开(公告)号：US20140167161A1
公开(公告)日：2014-06-19
申请号：US13713393
申请日：2012-12-13
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7841 , H01L29/66545 , H01L29/78654
摘要： Methods of forming a floating body cell (FBC) with faster programming and lower refresh rate and the resulting devices are disclosed. Embodiments include forming a silicon on insulator (SOI) layer on a substrate; forming a band-engineered layer surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions.
摘要翻译：公开了具有更快编程和更低刷新率的浮体单元（FBC）的形成方法以及所得到的器件。实施例包括在基板上形成绝缘体上硅（SOI）层; 形成围绕和/或在SOI层上的带工程层; 形成源极区域和漏极区域，所述源极区域和漏极区域中的至少一个在所述带状工程化层上; 以及在SOI层上，在源区和漏区之间形成栅极。

89. 发明申请

US20140138605A1 COMPACT LOCALIZED RRAM CELL STRUCTURE REALIZED BY SPACER TECHNOLOGY 有权
标题翻译：紧凑的本地化RRAM细胞结构由间隔技术实现
公开(公告)号：US20140138605A1
公开(公告)日：2014-05-22
申请号：US13683779
申请日：2012-11-21
申请人： Shyue Seng TAN , Eng Huat TOH , Elgin QUEK
发明人： Shyue Seng TAN , Eng Huat TOH , Elgin QUEK
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2445 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1675 , H01L45/1691
摘要： An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode.
摘要翻译：公开了一种具有垂直BJT选择器的RRAM。实施例包括在衬底中限定STI区域，在衬底中注入掺杂剂以在STI区域的底部周围和下方形成第一极性，在STI区域的相对侧上的阱上的第二极性沟道，以及第一在衬底的表面上的每个通道上的极性有源区域，在有源区域和STI区域上形成RRAM衬垫，在RRAM衬垫上形成牺牲顶部电极，在牺牲顶部电极的相对侧上形成间隔物，注入第二极性在牺牲顶部电极的相对侧上的有源区域中形成掺杂剂，在间隔物附近形成氧化硅，去除形成空腔的牺牲顶部电极的至少一部分，在空腔中形成邻近间隔物的内部间隔物和顶部电极。

90. 发明授权

US08674457B2 Methods to reduce gate contact resistance for AC reff reduction 有权
标题翻译：减少AC降低栅极接触电阻的方法
公开(公告)号：US08674457B2
公开(公告)日：2014-03-18
申请号：US12806354
申请日：2010-08-11
申请人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
发明人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.
摘要翻译：制造半导体器件的方法（和半导体器件）提供具有降低的栅极接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。在金属栅极电极和栅极接触层之间的杂质区域中将杂质注入或沉积在栅极堆叠中。执行退火处理，其将杂质区域转换成偏析层，其降低金属栅电极（例如，硅化物）和栅极接触层（例如非晶硅）之间的界面的肖特基势垒高度（SBH）。这导致较低的栅极接触电阻并有效降低器件的AC Reff。

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