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81. 发明申请

WO2008054969A1 THIN, PASSIVE COOLING SYSTEM 审中-公开
标题翻译：薄，被动冷却系统
公开(公告)号：WO2008054969A1
公开(公告)日：2008-05-08
申请号：PCT/US2007/081041
申请日：2007-10-11
申请人： APPLE INC. , ALI, Ihab A.
发明人： ALI, Ihab A.
IPC分类号： G06F1/20
CPC分类号： G06F1/203 , H05K7/20481 , H05K7/20518
摘要： A system includes a power source and a heat-shield mechanism which encloses the power source. This heat-shield mechanism includes a 3-dimensional housing that defines a cavity in which the power source resides, and a plate that is positioned to cover an opening to the cavity that is defined by an edge of the housing. Note that the housing contains three layers in which a second layer is sandwiched between a first layer and a third layer. This second layer has a first anisotropic thermal conductivity. Furthermore, the plate includes a material having a second anisotropic thermal conductivity.
摘要翻译：系统包括电源和封闭电源的隔热机构。该热屏蔽机构包括限定电源所在的空腔的三维壳体，以及定位成覆盖由壳体的边缘限定的空腔的开口的板。注意，壳体包含三层，其中第二层夹在第一层和第三层之间。该第二层具有第一各向异性热导率。此外，该板包括具有第二各向异性热导率的材料。

82. 发明申请

WO2008042573A3 EFFICIENT STORE QUEUE ARCHITECTURE 审中-公开
公开(公告)号：WO2008042573A3
公开(公告)日：2008-04-10
申请号：PCT/US2007/078351
申请日：2007-09-13
申请人： SUN MICROSYSTEMS, INC. , CYPHER, Robert E. , CHAUDHRY, Shailender
发明人： CYPHER, Robert E. , CHAUDHRY, Shailender
IPC分类号： G06F9/38 , G11C15/04
摘要： One embodiment of the present invention provides a store queue that applies the stores to a memory subsystem in program order. This store queue includes a content-addressable memory (CAM), which holds pending stores and facilitates looking up stores based on addresses for the stores, wherein the CAM does not keep track of program order between stores to different addresses. The store queue also includes a program-order queue which keeps track of program order between the stores in the CAM and thereby facilitates applying the stores to the memory subsystem in program order. In a variation on this embodiment, the CAM is a priority CAM which holds separate copies of multiple stores with identical addresses, and when a lookup based on an address matches multiple stores, returns the youngest matching store.

83. 发明申请

WO2007030323A2 DETECTING DEGRADATION OF COMPONENTS DURING RELIABILITY-EVALUATION STUDIES 审中-公开
标题翻译：在可靠性评估研究中检测组分的降解
公开(公告)号：WO2007030323A2
公开(公告)日：2007-03-15
申请号：PCT/US2006/032883
申请日：2006-08-22
申请人： SUN MICROSYSTEMS, INC. , VACAR, Dan , GROSS, Kenny, C. , MCELFRESH, David, K. , LOPEZ, Leoncio, D.
发明人： VACAR, Dan , GROSS, Kenny, C. , MCELFRESH, David, K. , LOPEZ, Leoncio, D.
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G01R31/2849 , G06F11/008 , G06F11/24
摘要： One embodiment of the present invention provides a system that determines the reliability of a component in a system. During operation, the system monitors inferential variables associated with a number of specimens of the component. The system then collects degradation data by first computing a likelihood value that indicates whether an inferential variable associated with a specimen of the component is behaving normally or abnormally. Next, the system determines whether the specimen of the component has degraded based on the likelihood value. If the specimen of the component is determined to have degraded, the system records the time when the specimen of the component was determined to have degraded. The system also uses the degradation data to determine the reliability of the component in the system.
摘要翻译：本发明的一个实施例提供了一种确定系统中的组件的可靠性的系统。在操作过程中，系统会监测与部件的多个样本相关的推理变量。系统然后通过首先计算可能性值来收集退化数据，所述可能性值指示与组件的样本相关联的推理变量是否正常或异常行为。接下来，系统基于似然值确定组件的样本是否已经劣化。如果确定组件的样本已经退化，则系统记录组件的样本确定已经退化的时间。系统还使用降级数据来确定系统中组件的可靠性。

84. 发明申请

WO2007015731A1 REDUCING UNCERTAINTY IN SEVERELY QUANTIZED TELEMETRY SIGNALS 审中-公开
标题翻译：在严格量化的电报信号中减少不确定度
公开(公告)号：WO2007015731A1
公开(公告)日：2007-02-08
申请号：PCT/US2006/025623
申请日：2006-06-29
申请人： SUN MICROSYSTEMS, INC. , URMANOV, Aleksey M. , GROSS, Kenny C.
发明人： URMANOV, Aleksey M. , GROSS, Kenny C.
IPC分类号： G01D3/08
CPC分类号： G01D3/08
摘要： A system that facilitates reducing uncertainty in a quantized signal. During operation, the system measures a quantized output signal from a sensor. Next, the system obtains an initial value for an uncertainty interval for the quantized output signal. The system then margins the quantized output signal high by introducing a controlled increase in the mean of the quantized output signal to produce a high-margined quantized output signal. Next, the system measures the high-margined quantized output signal from the sensor. The system then uses information obtained from the high-margined quantized output signal to reduce the uncertainty interval for the quantized output signal.
摘要翻译：有助于减少量化信号的不确定性的系统。在操作期间，系统测量来自传感器的量化输出信号。接下来，系统获得用于量化输出信号的不确定性间隔的初始值。然后，通过引入量化输出信号的平均值的受控增加以产生高边缘化的量化输出信号，系统然后使量化的输出信号为高。接下来，系统测量来自传感器的高边缘量化的输出信号。然后，系统使用从高边距量化输出信号获得的信息来减小量化输出信号的不确定性间隔。

85. 发明申请

WO2006101572A2 THE GENERATION OF MULTIPLE CHECKPOINTS IN A PROCESSOR THAT SUPPORTS SPECULATIVE EXECUTION 审中-公开
标题翻译：在支持实施执行的处理器中生成多个检查点
公开(公告)号：WO2006101572A2
公开(公告)日：2006-09-28
申请号：PCT/US2006/000355
申请日：2006-01-05
申请人： SUN MICROSYSTEMS, INC. , CHAUDHRY, Shailender , TREMBLAY, Marc , CAPRIOLI, Paul
发明人： CHAUDHRY, Shailender , TREMBLAY, Marc , CAPRIOLI, Paul
IPC分类号： G06F9/38
CPC分类号： G06F9/3863 , G06F9/383 , G06F9/3842
摘要： One embodiment of the present invention provides a system which creates multiple checkpoints in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during an instruction which causes a processor to enter execute-ahead mode, the system performs an initial checkpoint and commences execution of instructions in execute-ahead mode. Upon encountering a predefined condition during execute- ahead mode, the system generates an additional checkpoint and continues to execute instructions in execute-ahead mode. Generating the additional checkpoint allows the processor to return to the additional checkpoint, instead of the previous checkpoint, if the processor subsequently encounters a condition that requires the processor to return to a checkpoint. Returning to the additional checkpoint prevents the processor from having to re-execute instructions between the previous checkpoint and the additional checkpoint.
摘要翻译：本发明的一个实施例提供一种在支持推测执行的处理器中创建多个检查点的系统。系统以正常执行模式在程序执行期间以程序顺序发出指令来开始。在使处理器进入执行模式的指令期间遇到启动条件时，系统执行初始检查点并以执行提前模式开始执行指令。在执行预先模式期间遇到预定义的条件时，系统生成附加检查点，并以执行提前模式继续执行指令。如果处理器随后遇到需要处理器返回到检查点的条件，则生成附加检查点将允许处理器返回到附加检查点，而不是先前检查点。返回到附加检查点可防止处理器重新执行上一个检查点和附加检查点之间的指令。

86. 发明申请

WO2006086755A3 ACTIVATING A NON-ISOMETRIC FUNCTIONAL MOVEMENT THROUGH ELECTRICAL STIMULATION 审中-公开
公开(公告)号：WO2006086755A3
公开(公告)日：2006-08-17
申请号：PCT/US2006/004969
申请日：2006-02-10
申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA , PERUMAL, Ramu , WEXLER, Anthony S. , BINDER-MACLEOD, Stuart , DING, Jun
发明人： PERUMAL, Ramu , WEXLER, Anthony S. , BINDER-MACLEOD, Stuart , DING, Jun
IPC分类号： A61N1/18
摘要： One embodiment of the present invention provides a system that activates a muscle to produce a functional movement in a subject through electrical stimulation. During operation, the system first obtains a non isometric model which defines a functional movement associated with the muscle in response to electrical stimulation of the muscle. Next, the system uses the non isometric model to compute an electrical stimulation which produces a desired functional movement in the subject. The system then applies the computed electrical stimulation to the muscle to produce the desired functional movement in the subject.

87. 发明申请

WO2006007075A2 SELECTIVELY PERFORMING FETCHES FOR STORE OPERATIONS DURING SPECULATIVE EXECUTION 审中-公开
标题翻译：选择性地执行储存运营期间的投注
公开(公告)号：WO2006007075A2
公开(公告)日：2006-01-19
申请号：PCT/US2005/016434
申请日：2005-05-11
申请人： SUN MICROSYSTEMS, INC. , CHAUDHRY, Shailender , TREMBLAY, Marc , CAPRIOLI, Paul
发明人： CHAUDHRY, Shailender , TREMBLAY, Marc , CAPRIOLI, Paul
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3834 , G06F12/0862
摘要： One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.
摘要翻译：本发明的一个实施例提供了一种处理器，其在推测执行期间选择性地提取用于存储指令的高速缓存行。在正常执行期间，处理器按程序顺序发出执行指令。在遇到产生启动条件的指令时，处理器执行检查点并开始以推测执行模式执行指令。在推测执行模式期间遇到存储指令时，处理器检查L1数据高速缓存以寻找匹配的高速缓存行，并检查存储的存储缓冲区以匹配高速缓存行。如果匹配高速缓存行已经存在于L1数据高速缓存中，或者如果到匹配高速缓存行的存储已存在于存储缓冲区中，则处理器会抑制生成高速缓存行的提取。否则，处理器会为缓存行生成一个提取。

88. 发明申请

WO2005121712A3 METHOD AND APPARATUS FOR AUTOMATICALLY GENERATING AIRFOIL PERFORMANCE TABLES 审中-公开
公开(公告)号：WO2005121712A3
公开(公告)日：2005-12-22
申请号：PCT/US2004/040377
申请日：2004-12-02
申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA , VAN DAM, Cornelis P. , MAYDA, Edward A. , STRAWN, Roger Clayton
发明人： VAN DAM, Cornelis P. , MAYDA, Edward A. , STRAWN, Roger Clayton
IPC分类号： G01F19/00
摘要： One embodiment of the present invention provides a system that facilitates automatically generating a performance table for an object, wherein the object is subject to fluid flow. The system operates by first receiving a description of the object and testing parameters for the object. The system executes a flow solver using the testing parameters and the description of the object to produce an output. Next, the system determines if the output of the flow solver indicates negative density or pressure. If not, the system analyzes the output to determine if the output is converging. If converged, the system writes the output to the performance table for the object.

89. 发明申请

WO2005112394A1 ACCESS CONTROL FOR REQUESTED WEB OBJECTS BASED ON HTTP VALIDATION 审中-公开
标题翻译：基于HTTP验证的所请求的WEB对象的访问控制
公开(公告)号：WO2005112394A1
公开(公告)日：2005-11-24
申请号：PCT/US2005/010245
申请日：2005-03-25
申请人： ORACLE INTERNATIONAL CORPORATION , DESAI, Ajay , LEI, Ming , GOELL, Ric , JACOBS, Lawrence
发明人： DESAI, Ajay , LEI, Ming , GOELL, Ric , JACOBS, Lawrence
IPC分类号： H04L29/06
CPC分类号： H04L63/101 , H04L67/02 , H04L67/2842 , H04L69/329
摘要： One embodiment of the present invention provides a system that facilitates serving data from a cache server (102). The system operates upon receiving a request for the data at the cache server (402). The system first determines if the request requires access control (406), and also if the data is available in the cache (404). If the request requires access control and if the data is available in the cache, the system sends an authorization request to an origin server (408). Upon receiving a response from the origin server (410), the system determines if the response is an authorization (412). If so, the system sends the data to the requester (414).
摘要翻译：本发明的一个实施例提供一种便于从缓存服务器（102）提供数据的系统。系统在高速缓存服务器（402）接收到数据请求时操作。系统首先确定请求是否需要访问控制（406），以及数据是否在高速缓存（404）中可用。如果请求需要访问控制，并且如果数据在缓存中可用，则系统向原始服务器发送授权请求（408）。在从源服务器（410）接收到响应后，系统确定响应是否是授权（412）。如果是这样，系统将数据发送给请求者（414）。

90. 发明申请

WO2005106648A2 ENTERING SCOUT-MODE WHEN SPECULATIIVE STORES EXCEED THE CAPACITY OF THE STORE BUFFER 审中-公开
标题翻译：当商店存储超过存储缓冲区的容量时进入SCOUT模式
公开(公告)号：WO2005106648A2
公开(公告)日：2005-11-10
申请号：PCT/US2005/012110
申请日：2005-04-08
申请人： SUN MICROSYSTEMS, INC. , CHAUDHRY, Shailender , TREMBLAY, Marc , CAPRIOLI, Paul
发明人： CHAUDHRY, Shailender , TREMBLAY, Marc , CAPRIOLI, Paul
IPC分类号： G06F9/38
CPC分类号： G06F9/3863 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3865
摘要： One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store. If the number of stores that are encountered during execute-ahead mode exceeds the capacity of the store buffer, which means that the store buffer will never have additional space to accept additional stores during the execute-ahead mode because the store buffer is gated, the system directly enters scout mode, without waiting for the deferred queue to eventually fill.
摘要翻译：本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。在正常执行模式下，系统以程序顺序发出执行指令。在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。接下来，系统以执行模式执行指令和后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中以程序顺序执行其他非延迟指令。在执行提前模式期间遇到存储器时，系统确定存储缓冲区是否已满。如果是这样，系统将预取商店的高速缓存线，并延迟商店的执行。如果在执行超前模式期间遇到的存储的数量超过了存储缓冲区的容量，这意味着由于存储缓冲区被选通，在执行提前模式下，存储缓冲区将永远不会有额外的空间来接受附加存储，系统直接进入侦察模式，无需等待延期队列最终填满。

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