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81. 发明专利

CA2329423A1 REAL TIME DEBUGGER INTERFACE FOR EMBEDDED SYSTEMS 未知
公开(公告)号：CA2329423A1
公开(公告)日：1999-10-28
申请号：CA2329423
申请日：1999-04-14
申请人： TRANSWITCH CORP
发明人： PARRELLA EUGENE L , HEMBROOK PAUL , MARIANO RICHARD , ROY SUBHASH C
IPC分类号： G06F11/28 , G06F11/36 , G06F9/00
摘要： A debugging interface (10) includes a pair of decoders (28a, 28b) and an eve nt history buffer (14) coupled to the sequencer of a processor. The first decod er is coupled to the instruction RAM of the processor. The second decoder (32a) is coupled to the cause register (22a) of the sequencer and the event histor y buffer (14) is also coupled to the cause register (22a). The first decoder (28a) provides a three bit real time output (30a) which is indicative of the processor activity on a cycle by cycle basis. The three bit output (30a) indicates seven different conditions: whether the last instruction executed by the processor was an inc, an exception, an exception with no event history buffer entry, or a branch taken, whether there has been no instruction executed since the last clock cycle, and whether a jump was an immediate jum p or a jump to a register. The event history buffer (14) is loaded with more detailed information about the instruction last executed when the first decoder (28a) indicates that the last instruction was an exception or a jump to a register, and when there is a change in state of an interrupt line or a n internal processor exception.

82. 发明专利

IL113969A Apparatus and method for limiting jitter caused by pointer movement while mapping one telecommunications signal into another such signal 未知
公开(公告)号：IL113969A
公开(公告)日：1998-10-30
申请号：IL11396995
申请日：1995-06-01
申请人： TRANSWITCH CORP , ECI TELECOM
IPC分类号： H04J3/06 , H04J3/07 , H04J3/04
摘要： Jitter is limited in the mapping of a first telecommunications signal into a second telecommunications signal, by, upon receiving an indication that the payload pointer of the second telecommunications signal is moving in a first direction, generating a compensative payload pointer movement of the first telecommunications signal in a second direction which is opposite the first direction. The invention has particular application to the mapping of three E3 telecommunications signals which are in the format of a TUG-3 signal into an STS-3C SONET telecommunications signal in the STM-1 VC-4 format. When the STS-3C signal requires a pointer movement due to frequency compensation in the system, a compensative pointer movement at the TUG-3 level avoids eight units of jitter in the TUG-3 signal which could adversely affect system performance.

83. 发明专利

CA2113540C SYSTEM FOR CROSS-CONNECTING HIGH SPEED DIGITAL SONET SIGNALS 未知
公开(公告)号：CA2113540C
公开(公告)日：1998-09-22
申请号：CA2113540
申请日：1989-12-08
申请人： TRANSWITCH CORP
发明人： UPP DANIEL C , COCHRAN WILLIAM T
IPC分类号： H04B10/27 , H04L12/66 , H04Q3/52 , H04Q11/04 , H04B10/20
摘要： A modular, expandable, non-blocking system for cross-connecting high speed digital signals is provided. The system is capable of connecting DSn, CEPTn, and STSn signals as desired, with lower rate signals being included as components of the high-rate signals or terminating on low speed lines, as desired. The system accomplishes its goals by converting all incoming signals into a substantially SONET format, and by processing all the signals in that format. The signals are typically cross-connected in the substantially SONET format, although an expandable non-blocking wide band cross-connect module provided which cross-connects any like signals. If the outgoing signal is to be in other than SONET format, the substantially SONET formatted signal is reconverted into its outgoing format, To create a complete system, various modules are utilized, including: add/drop multiplexer means for add/drop applications of DS-0, DS-1, CEPTn signals, etc.; a SONET bus interface; a virtual tributary cross-connect module which cross-connects virtual tributary payloads in space, time, and phase to generate new substantially SONET formatted signals; a wide band cross-connect module; a DS-3/SONET converter; and front end interfaces including a DS-3 line interface, and various STSn interfaces. The modules may be mixed and matched as desired to accommodate a multitude of applications.

84. 发明专利

CA2170602A1 ASYNCHRONOUS DATA TRANSFER AND SOURCE TRAFFIC CONTROL SYSTEM 未知
公开(公告)号：CA2170602A1
公开(公告)日：1995-03-30
申请号：CA2170602
申请日：1994-09-20
申请人： TRANSWITCH CORP
发明人： UPP DANIEL C
IPC分类号： G06F13/362 , H04L12/403 , H04L12/56 , H04Q11/04
摘要： An asynchronous data transfer and source traffic control system includes a bus master (100) and a plurality of bus users (112, 114, 116) coupled to a bidirectional data bus (120-128). The bus master (100) provides two clock signals (120, 122) to each bus user (112, 114, 116), a system clock (120) and a frame clock (122). The frame clock designates the start of a frame. A frame format preferably includes fifteen or sixteen system clock cycles, the first of which is designated the request field and the last of which includes a grant field. One or more other cycles may be assigned control and/or routing information and the remainder of the cycles comprise a data field of fixed length. During the request field, any number of bus users (112, 114, 116) may request access which is received by the bus master (100). During the grant field the bus master (100) grants access to a selected bus user (112, 114, 116) for the entire data portion of the next frame. Which user (112, 114, 116) is granted access to the next frame is determined according to an arbitration algorithm in the bus master (100) which may be unknown to the bus users (112, 114, 116). The asynchronous data transfer and source traffic control system has particular application in accommodating the transfer of the contents of ATM cells used in BISDN systems.

85. 发明专利

CA2130473A1 METHODS AND APPARATUS FOR RETIMING AND REALIGNMENT OF STS-1 SIGNALS INTO STS-3 TYPE SIGNAL 未知
公开(公告)号：CA2130473A1
公开(公告)日：1993-09-16
申请号：CA2130473
申请日：1993-03-09
申请人： TRANSWITCH CORP
发明人： PARRUCK BIDYUT , HAMLIN ROBERT W JR
IPC分类号： H04J3/07 , G06F5/10 , G06F5/12 , H04J3/00 , H04J3/06 , H04J3/16 , H04L25/05 , H04J14/08 , H04L7/04
摘要： The SPE of an incoming STS-3 type signal is demultiplexed into three STS-1 payloads and fed to three FIFOs (45-1, 45-2, 45-3), and a byte which is synchronous with the TOH is tracked through the three FIFOs (45-1, 45-2, 45-3) to provide an indica- tion of the FIFO depth. A frame count is also kept to track the number of frames since a last pointer movement. Stuffs or destuffs are generated based on the FIFO depth as well as based on the frame count, with a stuff or destuff generated as quickly as four frames from a previous pointer movement if the FIFO is close to full or clos e to empty, and less quickly (e.g., at thirty-two frames from a previous pointer movement) if the FIFO is only starting to empty or t o fill. Where the STS-3 type signal is an STS-3C sig- nal, the decision on whether to stuff or destuff is made with reference to a ll three depth measurement circuits (48-1, 48.2, 48-3) as all the STS-1 payloads must be stuffed or destuffed together.

86. 发明专利

AU3242393A Digital clock dejitter circuits for regenerating clock signals with minimal jitter 未知
公开(公告)号：AU3242393A
公开(公告)日：1993-07-19
申请号：AU3242393
申请日：1992-12-08
申请人： TRANSWITCH CORP
发明人： UPP DANIEL C , WOLVAVER DAN H
IPC分类号： G06F5/06 , H04J3/00 , H04J3/07 , H04J3/16 , H04L7/02 , H04L7/00 , H04L25/36

87. 发明公开

EP1782542A4 METHODS AND APPARATUS FOR ERROR CORRECTION OF TRANSPARENT GFP (GENERIC FRAMING PROCEDURE) SUPERBLOCKS 审中-公开
标题翻译：方法和设备进行纠错透明GFP超级块
公开(公告)号：EP1782542A4
公开(公告)日：2008-08-13
申请号：EP05791554
申请日：2005-08-22
申请人： TRANSWITCH CORP
发明人： BHATTACHARYA SANTANU , GUPTA NEERAJ , MITTAL YOGESH , DARSHINI PRIYA , MUKHOPADHYAY SUVHASIS
IPC分类号： H03M13/15
CPC分类号： H03M13/1555 , H03M13/09 , H03M13/1545 , H03M13/1575
摘要： Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8x8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the CRC remainder is compared to a single bit error syndrome table and if an error is located, it is corrected. In the second stage, the CRC remainder is compared to a double bit error syndrome table and if an error is located, it is corrected. The third stage corrects the second error of a double bit error. The flag byte is processed first, followed by the data bytes, eight bytes at a time.

88. 发明公开

EP1510049A4 METHODS AND APPARATUS FOR GUARANTEEING A MINIMUM CELL RATE (MCR) FOR ASYNCHRONOUS TRANSFER MODE (ATM) TRAFFIC QUEUES 有权
标题翻译：方法和设备保证最低速率的细胞（MCR）车辆交通流的异步传输模式队列（ATM）
公开(公告)号：EP1510049A4
公开(公告)日：2005-08-31
申请号：EP03734003
申请日：2003-05-13
申请人： TRANSWITCH CORP
发明人： NOVICK RONALD P
IPC分类号： H04L12/56 , H04L29/06
CPC分类号： H04L47/6215 , H04L12/5601 , H04L12/5602 , H04L29/06 , H04L47/50 , H04L47/562 , H04L47/566 , H04L69/28 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681
摘要： An apparatus for guaranteeing MCR in an ATM device includes at least one queue (12) for each service category, a scheduler (18) for dequeuing cells from the queues, a queue status block (20) for indicating which queues are empty, and an MCR service block (22). The MCR service block includes a plurality of timers, at least one for each service category. According to the methods of the invention, and MCR value is selected for each queue (or service category) and a timer in the MCR service block is set according to the MCR value. The scheduler dequeues cells in strict priority from non-empty queues as determined by the queue status block. The scheduler is preempted, however, by the MCR service block when a queue fails to be serviced before its associated timer expires.
摘要翻译：在ATM装置在保证MCR的装置包括：对于每个服务类别的至少一个队列，用于从所述队列中出队的细胞，用于指示队列队列状态块是空的，并且在MCR服务块的调度器。的MCR服务块包括定时器的复数，至少一个用于每个服务类别。。根据在MCR值的本发明的方法被选择用于每个队列（或服务类别）和MCR服务块设置计时器雅丁到MCR值。调度器从队列中严格的优先级细胞与非空队列为确定性由队列状态块开采。当队列失败其相关联的定时器到期之前被服务调度器被抢占，然而，由MCR服务块。队列和相关联的定时器的配置受到替代实施例。

89. 发明公开

EP1287644A4 METHOD AND APPARATUS FOR THE FAIR AND EFFICIENT TRANSFER OF VARIABLE LENGTH PACKETS USING FIXED LENGTH SEGMENTS 审中-公开
标题翻译：方法和装置公正，得到的不同长度的包IN USE固定长度段的有效传送
公开(公告)号：EP1287644A4
公开(公告)日：2003-07-02
申请号：EP01923086
申请日：2001-04-03
申请人： TRANSWITCH CORP
发明人： LAU JOSEPH C , ROY SUBHASH C , GILSDORF JOHN F
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/28 , H04L12/58
CPC分类号： H04Q11/0478 , H04L2012/5652
摘要： A method for the fair and efficient transfer of variable length packets using fixed length "segments" utilizes a modified UTOPIA interface (12) with three additional signals (14,16,18) added, i.e. start of packet (SOP), end of packet (EOP), and most significant byte (MSB). Packets are broken into "segments" of fixed length. The start of a segment is marked by a pulse on the UTOPIA start of cell (SOC) signal line. The start of a packet is marked by a pulse on the SOP signal line (14). The end of a packet is marked by a pulse on the EOP signal line (16). When a packet ends with a single byte on the bus, the MSB signal line (18) is asserted to distinguish it from a packet which ends with two bytes on the bus. The invention can be expanded to accommodate buses wider than 16-bits by making the EOP a multiple bit signal.

90. 发明公开

EP0724796A4 ASYNCHRONOUS DATA TRANSFER AND SOURCE TRAFFIC CONTROL SYSTEM 失效
标题翻译：系统进行异步数据传输和控制源流量
公开(公告)号：EP0724796A4
公开(公告)日：1999-11-24
申请号：EP94929268
申请日：1994-09-20
申请人： TRANSWITCH CORP
发明人： UPP DANIEL C
IPC分类号： G06F13/362 , H04L12/403 , H04L12/56 , H04Q11/04
CPC分类号： H04L12/5601 , H04L12/403 , H04L12/4035 , H04L2012/5613 , H04L2012/5615 , H04L2012/5679 , H04Q11/0478
摘要： An asynchronous data transfer and source traffic control system includes a bus master (100) and a plurality of bus users (112, 114, 116) coupled to a bidirectional data bus (120-128). The bus master (100) provides two clock signals (120, 122) to each bus user (112, 114, 116), a system clock (120) and a frame clock (122). The frame clock designates the start of a frame. A frame format preferably includes fifteen or sixteen system clock cycles, the first of which is designated the request field and the last of which includes a grant field. One or more other cycles may be assigned control and/or routing information and the remainder of the cycles comprise a data field of fixed length. During the request field, any number of bus users (112, 114, 116) may request access which is received by the bus master (100). During the grant field, the bus master (100) grants access to a selected bus user (112, 114, 116) for the entire data portion of the next frame. Which user (112, 114, 116) is granted access to the next frame is determined according to an arbitration algorithm in the bus master (100) which may be unknown to the bus users (112, 114, 116). The asynchronous data transfer and source traffic control system has particular application in accommodating the transfer of the contents of ATM cells used in BISDN systems.

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